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| the following document contains information on cypress products. the document has the series name, product name, and ordering part numbering with the prefix mb. however, cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix cy. how to check the ordering p art n umber 1. g o to www.cypress.com/pcn . 2. enter the keyword ( for example , ordering part number) i n the search pcns field and click apply . 3. click the corresponding title from the search results. 4. download the affected parts list file , which has details of all changes for more information please contact your local sales office for additional information about cypress products and solutions. about cypress cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. cypress' microcontrollers, analog ics, wireless and usb - based connectivity solutions and reliable, high - performance memories help engineers design differentiated products and get them to market first. cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrup t markets by creating new product categories in record time. to learn more, go to www.cypress.com .
mb91590 series fr family fr81s 32 - bit microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408-943 - 2600 document number: 002- 04727 rev. *b revised december 1, 2017 this series is cypress 32 - bit microcontroller designed for automotive and industrial control applications. it contains the fr81s cpu that is compatible with the fr family. the fr81s has a high level performance among the cypress fr family by enhancing cpu instruction pipeline and load store processing, and improving internal bus transfer. it is best suited for application control for automotive . f eatures fr81s cpu core ? 32- bit risc, load/store architecture, pipeline 5- stage structure ? max imum operating frequency : 128 mhz (sourc e oscillation = 4.0 mhz and 32 multiplied (pll clock multiplication system)) it shows maximum cpu frequency of series. the specification of each part number can be referred in ? product lineup ? and ? electrical characteristics .? ? general - purpose register : 32 bits 16 sets ? 16- bit fixed length instructions (basic instruction), 1 instruction per cycle ? instructions appropriate to embedded applications ? memory -to - memory transfer instruction ? bit processing instruction ? barrel shift instruction etc. ? high - level language support instructions ? function entry/exit instructions ? register content multi - load and store instructions ? bit search instructions ? logical 1 detection, 0 detection, and change - point detection ? branch instructions with delay slot ? reduced overhead duri ng branch process ? register interlock function ? easy assembler writing ? the support at the built - in / instruction level of the multiplier ? signed 32 - bit multiplication : 5 cycles ? signed 16 - bit multiplication : 3 cycles ? interrupt (pc/ps saving) ? 6 cycles (16 pri ority levels) ? the harvard architecture allows simultaneous execution of program and data access. ? instruction compatibility with the fr family ? built - in memory protection function (mpu) ? eight protection areas can be specified commonly for instructions and th e data. ? control access privilege in both privilege mode and user mode. ? built - in fpu (floating point arithmetic) ? ieee754 compliant ? floating - point register 32- bit 16 sets peripheral functions ? clock generation (equipped with sscg function) ? main oscillation (4mhz) ? sub oscillation (32khz) or none sub oscillation ? pll multiplication rate : 1 to 32 times ? built - in program flash memory capacity 2048 + 64kb (series maximum) ? built - in data flash memory capacity(workflash) 64kb ? built - in ram capacity ? main ram 192kb (series maximum) ? sub ram (on ahb) 64kb (series maximum) ? backup ram 8kb ? general - purpose ports (5v pin) : 63 (dual clock products : 61) ? included i 2 c pseudo open drain support ports : 4 ? general - purpose ports (3v pin) : 93 ? included 48 combined external bus i nterface (for gdc external memory i/f) ? external bus interface ? gdc external memory for i/f use ? 25- bit address, 16- bit data ? power supply voltage fixed to 3.3v ? dma controller ? up to 16 channels can be started simultaneously. ? 2 transfer factors (internal periph eral request and software) ? a/d converter ( successive approximation type) ? 8/10 - bit resolution : 32 channels ? conversion time : 3s ? external interrupt input: 16 channels ? level ("h" / "l"), or edge detection (rising or falling) enabled ? lin - uart ? 6 channels, ch. 2 to ch.7 ? uart, synchronous mode, lin - uart mode is selectable. ? lin protocol revision 2.1 is supported ? spi (serial peripheral interface) supported (synchronous mode) ? full - duplex double buffering system ? lin synch break detection (linked to the input capture) ? built - in dedicated baud rate generator ? dma transfer support document number: 002- 04727 rev. *b page 2 of 174 mb91590 series ? multi - function serial communication (built - in transmission/reception fifo memory) : ? 2 channels for mb91f591/2/4/6/7/9 ? 6 channels for mb91f59a/b < uart (asynchronous serial interface) > ? full -du plex double buffering system, 16 - byte transmission fifo memory, 16 - byte reception fifo memory ? parity or no parity is selectable . ? built - in dedicated baud rate generator ? an external clock can be used as the transfer clock ? parity, frame, and overrun error det ect functions provided ? dma transfer support document number: 002- 04727 rev. *b page 3 of 174 mb91590 series ? i/o relocation ? peripheral function pins can be reassigned. ? low - power consumption mode ? sleep / stop / watch / sub run mode ? stop (power shutdown) / watch (power shutdown) mode ? gdc part self - support power supply ? power on reset ? low - voltage detection reset(external low - voltage detection) ? low - voltage dete ction reset(internal low - voltage detection) ? gdc ? internal/memory frequency : 81mhz ? the resolution of the display which can support : 800 480 at the maximum screen overlay of five simultaneous layers at the maximum (window) size of the resolution which can be supported varies depending on color format. ? analog video input (ntsc) ? digital video input (rgb666/555) ? yuv input (bt.656) ? video image expansion/reduction /invert function is supported ? rgb digital output (6 - bit 3) ? built - in 2d rendering engine the line drawing is supported. the bitblt function is supported. display list operation is supported 8bpp indirect color argb - 1555 direct color alpha blending, anti - aliasing ? built - in sprite engine equipped with automatic display function when booted maximum of 512 sprites are supported 32 special sprites capable of automatic animation are supported. the command list execution is supported. 1bpp, 2bpp, 4bpp, 8bpp indirect color argb - 1555, rgb - 565, argb - 8888 direct color the color format for each sprite can be set. h orizontal invert, vertical invert alpha blending ? built - in memory ? 800kb(mb91f591/2/4/6/7/9) ? 1792kb(mb91f59a/b) ? hs - spi(mb91f59a/b) ? device package : lqfp - 208, hqfp - 208*, bga320, teqfp -208* ? cmos 90nm technology ? power supplies ? 5v/3.3v power supply ? the internal 1.2v is generated from 5v/3.3v with the voltage step - down circuit. ? i/o of an external bus and gdc, 3.3v power supply used. ? for other i/o, 5v power supply used. ? if 2 power supplies are used, they must turn on in the specified sequence (5v 3.3v ). *: under consideration. for detailed information about mount conditions, contact your sales representative. document number: 002- 04727 rev. *b page 4 of 174 mb91590 series contents 1. product lineup .................................................................................................................................................................. 5 2. pin assignment ............................................................................................................................................................... 11 2.1 pin assignment (mb91f591/2/4/6/7/9 single clock product) ...................................................................................... 11 2.2 pin assignment (mb91f591/2/4/6/7/9 dual clock product) ......................................................................................... 12 2.3 pin assignment (mb91f59a/b single clock product) ................................................................................................. 13 2.4 pin assignment (mb91f59a/b dual clock product) .................................................................................................... 14 2.5 pin assignment (bga product) ................................................................................................................................... 15 3. pin description ................................................................................................................................................................ 16 3.1 pin description of lqfp - 208/teqfp -208 ................................................................................................................... 16 3.2 mb91f59a/b (bga320) .............................................................................................................................................. 30 4. i/o circuit type ............................................................................................................................................................... 45 5. handling precautions ..................................................................................................................................................... 50 5.1 precautions for product design ................................................................................................................................... 50 5.2 precautions for package mounting .............................................................................................................................. 51 5.3 precautions for use environment ................................................................................................................................ 52 6. handling devices ............................................................................................................................................................ 53 7. block diagram ................................................................................................................................................................. 56 8. memory map .................................................................................................................................................................... 58 9. i/o map ............................................................................................................................................................................. 68 10. interrupt vect or table ................................................................................................................................................... 106 11. electrical characteristics ............................................................................................................................................. 109 11.1 absolute maximum ratings ....................................................................................................................................... 109 11.2 recommended operating conditions ....................................................................................................................... 111 11.3 dc characteristics .................................................................................................................................................... 112 11.4 ac characteristics ..................................................................................................................................................... 119 11.4.1 main clock timing ...................................................................................................................................................... 119 11.5 a/d converter ............................................................................................................................................................ 163 11.5.1 electrical characteristics ............................................................................................................................................ 163 11.5.2 definition of a/d converter terms ............................................................................................................................. 164 11.5.3 notes on using a/d converter ................................................................................................................................... 166 11.6 flash memory ............................................................................................................................................................ 167 11.6.1 electrical characteristics ............................................................................................................................................ 167 11.6.2 notes .......................................................................................................................................................................... 167 12. ordering information .................................................................................................................................................... 168 13. package dimensions .................................................................................................................................................... 169 14. major changes .............................................................................................................................................................. 172 document history ............................................................................................................................................................... 173 sales, solutions, and legal information ........................................................................................................................... 174 products .............................................................................................................................................................................. 174 psoc ? solutions ................................................................................................................................................................. 174 cypress deve loper community ......................................................................................................................................... 174 technical support .............................................................................................................................................................. 174 document number: 002- 04727 rev. *b page 5 of 174 mb91590 series 1. p roduct l ineup product item mb91f591b/bs mb91f591bh/bhs cpu core fr81s technology 90nm package lqfp208 sub clock yes (non - s series) no (s series) maximum cpu operating frequency 80mhz maximum gdc operating frequency 81mhz built - in cr oscillator 100khz system clock on chip pll flash main 576kb work 64kb ram main 40kb backup 8kb vram 260kb watchdog timer 1ch hardware 1ch software clock supervisor initial value "on" initial value "off" low - voltage detection reset (external low - voltage detection) yes low - voltage detection reset (internal low - voltage detection) yes nmi function yes dma controller 16ch can 1ch (64msg) 2ch (32msg) lin - uart 6ch multi - function serial interface 2ch a/d converter (8bit/10bit) 1unit/32ch reload timer(16bit) 4ch base timer(16bit) 2ch free - run timer(32bit) 2ch input capture(32bit) 6ch output compare(32bit) 4ch ppg timer(16bit) 24ch sound generator 5ch real - time clock yes external interrupt 16ch cr/sub compensation function yes crc generation yes stepping motor control 6ch stop mode (including power shut - off) supported power supply voltage micom : 4.5v to 5.5v gdc : 3.0v to 3.6v operating temperature - 40c to +105c allowable power [mw] 1250 others flash product on chip debugger yes document number: 002- 04727 rev. *b page 6 of 174 mb91590 series product item mb91f592b /bs mb91f592bh /bhs mb91f594b /bs mb91f594bh /bhs cpu core fr81s technology 90nm package lqfp208 sub clock yes (non - s series) no (s series) maximum cpu operating frequency 80mhz maximum gdc operating frequency 81mhz built - in cr oscillator 100khz system clock on chip pll flash main 576kb 1088kb work 64kb ram main 40kb 64kb backup 8kb vram 800kb watchdog timer 1ch hardware 1ch software clock supervisor initial value "on" initial value "off" initial value "on" initial value "off" low - voltage detection reset (external low - voltage detection) yes low - voltage detection reset (internal low - voltage detection) yes nmi function yes dma controller 16ch can 1ch (64msg) 2ch (32msg) lin - uart 6ch multi - function serial interface 2ch a/d converter (8bit/10bit) 1unit/32ch reload timer(16bit) 4ch base timer(16bit) 2ch free - run timer(32bit) 2ch input capture(32bit) 6ch output compare(32bit) 4ch ppg timer(16bit) 24ch sound generator 5ch real - time clock yes external interrupt 16ch cr/sub compensation function yes crc generation yes stepping motor control 6ch stop mode (including power shut - off) supported power supply voltage micom:4.5v to 5.5v gdc:3.0v to 3.6v operating temperature - 40c to +105c allowable power [mw] 1250 others flash product on chip debugger yes document number: 002- 04727 rev. *b page 7 of 174 mb91590 series product item mb91f596b /bs* mb91f596bh /bhs* mb91f597b /bs* mb91f597bh /bhs* cpu core fr81s technology 90nm package hqfp208 sub clock yes (non - s series) no (s series) maximum cpu operating frequency 128mhz maximum gdc operating frequency 81mhz built - in cr oscillator 100khz system clock on chip pll flash main 576kb work 64kb ram main 40kb backup 8kb vram 260kb 800kb watchdog timer 1ch hardware 1ch software clock supervisor initial value "on" initial value "off" initial value "on" initial value "off" low - voltage detection reset (external low - voltage detection) yes low - voltage detection reset (internal low - voltage detection) yes nmi function yes dma controller 16ch can 1ch (64msg) 2ch (32msg) lin - uart 6ch multi - function serial interface 2ch a/d converter (8bit/10bit) 1unit/32ch reload timer(16bit) 4ch base timer(16bit) 2ch free - run timer(32bit) 2ch input capture(32bit) 6ch output compare(32bit) 4ch ppg timer(16bit) 24ch sound generator 5ch real - time clock yes external interrupt 16ch cr/sub compensation function yes crc generation yes stepping motor control 6ch stop mode (including power shut - off) supported power supply voltage micom:4.5v to 5.5v gdc:3.0v to 3.6v operating temperature - 40c to +105c allowable power [mw] 2500 others flash product on chip debugger yes *: under consideration. for detailed information about mount conditions, contact your sales representative. document number: 002- 04727 rev. *b page 8 of 174 mb91590 series product item mb91f599b/bs* mb91f599bh/bhs* cpu core fr81s technology 90nm package hqfp208 sub clock yes (non - s series) no (s series) maximum cpu operating frequency 128mhz maximum gdc operating frequency 81mhz built - in cr oscillator 100khz system clock on chip pll flash main 1088kb work 64kb ram main 64kb backup 8kb vram 800kb watchdog timer 1ch hardware 1ch software clock supervisor initial value "on" initial value "off" low - voltage detection reset (external low - voltage detection) yes low - voltage detection reset (internal low - voltage detection) yes nmi function yes dma controller 16ch can 1ch (64msg) 2ch (32msg) lin - uart 6ch multi - function serial interface 2ch a/d converter (8bit/10bit) 1unit/32ch reload timer(16bit) 4ch base timer(16bit) 2ch free - run timer(32bit) 2ch input capture(32bit) 6ch output compare(32bit) 4ch ppg timer(16bit) 24ch sound generator 5ch real - time clock yes external interrupt 16ch cr/sub compensation function yes crc generation yes stepping motor control 6ch stop mode (including power shut - off) supported power supply voltage micom:4.5v to 5.5v gdc:3.0v to 3.6v operating temperature - 40c to +105c allowable power [mw] 2500 others flash product on chip debugger yes *: under consideration. for detailed information about mount conditions, contact your sales representative. document number: 002- 04727 rev. *b page 9 of 174 mb91590 series product item mb91f59ac /f59acs mb91f59ach /f59achs mb91f59bc /f59bcs mb91f59bch /f59bchs cpu core fr81s technology 90nm package bga320/teqfp - 208* 1 sub clock yes (non - s series) no (s series) maximum cpu operating frequency 128mhz maximum gdc operating frequency 81mhz built - in cr oscillator 100khz system clock on chip pll flash main 1600kb 2112kb work *2 64kb ram main 192kb sub on ahb 64kb backup 8kb vram 1792kb watchdog timer 1ch hardware 1ch software clock supervisor initial value "on" initial value "off" initial value "on" initial value "off" low - voltage detection reset (external low - voltage detection) yes low - voltage detection reset (internal low - voltage detection) yes nmi function yes dma controller 16ch can 1ch (64msg) 2ch (32msg) lin - uart 6ch multi - function serial interface 6ch *3 high speed spi (gdc) yes a/d converter (8bit/10bit) 1unit/32ch up/down counter(16bit) 3ch reload timer(16bit) 8ch base timer(16bit) 2ch free - run timer(32bit) 8ch input capture(32bit) 12ch output compare(32bit) 4ch ppg timer(16bit) 24ch sound generator 5ch real - time clock yes external interrupt 16ch cr/sub compensation function yes crc generation yes stepping motor control 6ch stop mode (including power shut - off) supported power supply voltage micom:4.5v to 5.5v gdc:3.0v to 3.6v operating temperature - 40c to +105c allowable power [mw] 2500 others flash product jtag boundary scan test yes (only support bga package products) on chip debugger yes document number: 002- 04727 rev. *b page 10 of 174 mb91590 series *1 :under consideration. *2 : start address of work flash memory is different between mb91f591/2/4/6/7/9 and mb91f59a/b. *3 : i 2 c is supported with ch.0 and ch.1 only. main difference of functionality between mb91f594 and mb91f59b part item mb91f594 mb91f59b mcu part flash (main) 1088kb 2112kb ram (main) 64kb 192kb ram (sub on ahb) - 64kb multi - function serial interface 2ch 6ch free - run timer 2ch 8ch input capture 6ch 12ch reload timer 4ch 8ch up/down counter - 3ch package lqfp208 bga320/teqpf - 208* jtag boundary scan test - yes (only support bga package products) gdc part vram 800kb 1792kb high speed spi - yes *: under consideration. document number: 002- 04727 rev. *b page 11 of 174 mb91590 series 2. pin assignment 2.1 pin assignment (mb91f591/2/4/6/7/9 single clock product ) (top view) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ppg6_2 ppg5_2 ppg0_1 ppg9_1 ppg4_2 ppg3_2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ppg7_2 - - - - - icu5_1 icu4_1 icu1_1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - tot2 tot1 tot0 tin3 tin2 tin1 tin0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - tot3 int7 int6 trg4 - - trg3 int8 int15 int11 - ppg0_2 - - - - - - - - cmdtrg - - - - - - - - - - - - - - - - vin7 vin6 vin5 vin4 vin3 vin2 vin1 vin0 - - - - - sck5 sot5 sin5 sck4 sot4 sin4 sck3 sot3 sin3 - - adtg - - - - - - - - dckin csout hsin vsin cclk bin7 bin6 bin5 bin4 bin3 bin2 - - gin7 gin6 gin5 gin4 gin3 gin2 rin7 rin6 rin5 rin4 rin3 rin2 - - - - - ocu0 frck0 frck1 sgo3 sga3 sgo2 sga2 wot sgo1 rx2 tx2 - vss avcc3 avss3 vin refout avr3 avss3 avcc3 pg0 pg3 pg2 pg1 ph3 pc7 pc6 pc5 pc4 pc3 pc2 vcc3 vss pb7 pb6 pb5 pb4 pb3 pb2 pa7 pa6 pa5 pa4 pa3 pa2 vcc3 vss vcc5 p136 p137 vss md2 p122 p121 p120 p117 p116 p115 p114 p097 p094 p113 p112 p090 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 - - - - - - vcc3 1 156 dvcc - - - - - - - - - - - rout2 pd2 2 155 dvss - - - - - - - - - - - rout3 pd3 3 154 p087 pwm2m5 an31 icu4_2 ppg23 - - - - - - - rout4 pd4 4 153 p086 pwm2p5 an30 icu3_2 ppg22 - - - - - - - rout5 pd5 5 152 p085 pwm1m5 an29 icu2_2 ppg21 - - - - - - - rout6 pd6 6 151 p084 pwm1p5 an28 icu1_2 ppg20 - - - - - - - rout7 pd7 7 150 p083 pwm2m4 an27 icu0_2 ppg19 - - - - - - - gout2 pe2 8 149 p082 pwm2p4 an26 sck6 ppg18 - - - - - - - gout3 pe3 9 148 p081 pwm1m4 an25 sot6 ppg17 - - - - - - - gout4 pe4 10 147 p080 pwm1p4 an24 sin6 ppg16 - - - - - - - gout5 pe5 11 146 dvcc - - - - - - - - - - - gout6 pe6 12 145 dvss - - - - - - - - - - - gout7 pe7 13 144 p077 pwm2m3 an23 sck7_1 ppg15_1 - - - - - - - bout2 pf2 14 143 p076 pwm2p3 an22 sot7_1 ppg14_1 - - - - - - - bout3 pf3 15 142 p075 pwm1m3 an21 sin7_1 ppg13_1 - - - - - - - bout4 pf4 16 141 p074 pwm1p3 an20 - ppg12_1 - - - - - - - bout5 pf5 17 140 p073 pwm2m2 an19 - - - - - - - - - - vcc3 18 139 p072 pwm2p2 an18 - - - - - - - - - - vss 19 138 p071 pwm1m2 an17 - - - - - - - - - - c_3 20 137 p070 pwm1p2 an16 - - - - - - - - - bout6 pf6 21 136 dvcc - - - - - - - - - - - bout7 pf7 22 135 dvss - - - - - - - - - - - dckout pg4 23 134 p067 pwm2m1 an15 - - - - - - - - - vsync pg5 24 133 p066 pwm2p1 an14 - - - - - - - - - hsync pg6 25 132 p065 pwm1m1 an13 - - - - - - - - - deout pg7 26 131 p064 pwm1p1 an12 - - - - - ppg0 tin0_2 sin2_1 d0 p000 27 130 p063 pwm2m0 an11 - - - - - ppg1 tin1_2 sot2_1 d1 p001 28 129 p062 pwm2p0 an10 - - - - - ppg2 tin2_2 sck2_1 d2 p002 29 128 p061 pwm1m0 an9 - - - - - ppg3 tin3_2 sin3_1 d3 p003 30 127 p060 pwm1p0 an8 - - - - - ppg4 tot0_2 sot3_1 d4 p004 31 126 dvcc - - - - - - - ppg5 tot1_2 sck3_1 d5 p005 32 125 dvss - - - - - - - ppg6 tot2_2 - d6 p006 33 124 c_1 - - - - - - - ppg7 tot3_2 - d7 p007 34 123 vss - - - - - - - - - - d8 p010 35 122 vcc5 - - - - - - - - - - - - vss 36 121 p107 sgo4_1 an7 - - - ppg5_1 - - - - - - vcc3 37 120 p106 sga4_1 an6 - - - ppg4_1 - - - rout0 d9 p011 38 119 p105 sck5_1 an5 tot1_1 - - ppg3_1 - - - rout1 d10 p012 39 118 p104 sot5_1 an4 tot0_1 - - ppg2_1 - - - gout0 d11 p013 40 117 p103 sin5_1 an3 tin3_1 - - ppg1_1 - - - gout1 d12 p014 41 116 p102 sck4_1 an2 tin2_1 - - ppg10 - - - bout0 d13 p015 42 115 p101 sot4_1 an1 tin1_1 - - ppg9 - - - bout1 d14 p016 43 114 p100 sin4_1 an0 tin0_1 - - ppg8 - - - - d15 p017 44 113 avss5/avrl5 - - - - - - - - - - wex p020 45 112 avrh5 - - - - - - - - - - cs0x p021 46 111 avcc5 - - - - - - - - - - cs1x p022 47 110 p125 ocu3 - - icu0 - ppg10_2 - - - - rex p023 48 109 p124 ocu2 - - icu5_2 - ppg9_2 - - - - - p024 49 108 p123 ocu1 - - - - ppg8_2 - - - - - p025 50 107 p096 rx0 - int9 - - - - - - - a00 p026 51 106 p095 tx0 - - - - ppg10_1 - - - - - - vss 52 105 vcc5 - - - - - - 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 vcc3 p027 p030 p031 p032 p033 p034 p035 p036 p037 p040 p041 p042 p043 p044 p045 p046 p047 vcc3 vss c_2 p050 p051 p052 p053 p054 p055 p056 p057 vss x1 x0 md1 md0 rstx vss vcc5 p126 p127 p130 p131 p132 p133 p134 nmix p091 p092 p093 p110 p111 debugif vss - a01 a02 a03 a04 a05 a06 a07 a08 a09 a10 a11 a12 a13 a14 a15 a16 a17 - - - a18 a19 a20 a21 a22 a23 a24 rdy - - - - - - - - trg0 - - trg1 - trg5 trg2 - sga0 sgo0 sga1 tx1 rx1 - - - - - - - - - - - - - - - - - - - - - - - - - - spi_do spi_di spi_sck spi_xcs - - - - - - - - - sin0 sot0 sck0 - - ppg11_1 ppg1_3 - sin2 sck2 sot2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - sin1 sot1 sck1 - - int12 int13 int14 - int10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - int1 - int0 int4 int2 int3 int5 - tot2_1 tot3_1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - icu1 icu2 icu3 icu4 icu5 - icu2_1 icu0_1 icu3_1 - - - - - - - - - - - - - - - - - - tioa0 tioa1 tiob0 tiob1 - - ppg6_1 ppg7_1 ppg8_1 ppg1_2 ppg2_2 - - fr+gdc top view lqfp-208 / hqfp-208 (single clock product) (single clock product) document number: 002- 04727 rev. *b page 12 of 174 mb91590 series 2.2 pin assignment (mb91f591/2/4/6/7/9 dual clock product ) (top view) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ppg6_2 ppg5_2 ppg0_1 ppg9_1 ppg4_2 ppg3_2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ppg7_2 - - - - - icu5_1 icu4_1 icu1_1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - tot2 tot1 tot0 tin3 tin2 tin1 tin0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - tot3 int7 int6 trg4 - - trg3 int8 int15 int11 - ppg0_2 - - - - - - - - cmdtrg - - - - - - - - - - - - - - - - vin7 vin6 vin5 vin4 vin3 vin2 vin1 vin0 - - - - - sck5 sot5 sin5 sck4 sot4 sin4 sck3 sot3 sin3 - - adtg - - - - - - - - dckin csout hsin vsin cclk bin7 bin6 bin5 bin4 bin3 bin2 - - gin7 gin6 gin5 gin4 gin3 gin2 rin7 rin6 rin5 rin4 rin3 rin2 - - - (x1a) (x0a) - - ocu0 frck0 frck1 sgo3 sga3 sgo2 sga2 wot sgo1 rx2 tx2 - vss avcc3 avss3 vin refout avr3 avss3 avcc3 pg0 pg3 pg2 pg1 ph3 pc7 pc6 pc5 pc4 pc3 pc2 vcc3 vss pb7 pb6 pb5 pb4 pb3 pb2 pa7 pa6 pa5 pa4 pa3 pa2 vcc3 vss vcc5 vss md2 p122 p121 p120 p117 p116 p115 p114 p097 p094 p113 p112 p090 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 - - - - - - vcc3 1 156 dvcc - - - - - - - - - - - rout2 pd2 2 155 dvss - - - - - - - - - - - rout3 pd3 3 154 p087 pwm2m5 an31 icu4_2 ppg23 - - - - - - - rout4 pd4 4 153 p086 pwm2p5 an30 icu3_2 ppg22 - - - - - - - rout5 pd5 5 152 p085 pwm1m5 an29 icu2_2 ppg21 - - - - - - - rout6 pd6 6 151 p084 pwm1p5 an28 icu1_2 ppg20 - - - - - - - rout7 pd7 7 150 p083 pwm2m4 an27 icu0_2 ppg19 - - - - - - - gout2 pe2 8 149 p082 pwm2p4 an26 sck6 ppg18 - - - - - - - gout3 pe3 9 148 p081 pwm1m4 an25 sot6 ppg17 - - - - - - - gout4 pe4 10 147 p080 pwm1p4 an24 sin6 ppg16 - - - - - - - gout5 pe5 11 146 dvcc - - - - - - - - - - - gout6 pe6 12 145 dvss - - - - - - - - - - - gout7 pe7 13 144 p077 pwm2m3 an23 sck7_1 ppg15_1 - - - - - - - bout2 pf2 14 143 p076 pwm2p3 an22 sot7_1 ppg14_1 - - - - - - - bout3 pf3 15 142 p075 pwm1m3 an21 sin7_1 ppg13_1 - - - - - - - bout4 pf4 16 141 p074 pwm1p3 an20 - ppg12_1 - - - - - - - bout5 pf5 17 140 p073 pwm2m2 an19 - - - - - - - - - - vcc3 18 139 p072 pwm2p2 an18 - - - - - - - - - - vss 19 138 p071 pwm1m2 an17 - - - - - - - - - - c_3 20 137 p070 pwm1p2 an16 - - - - - - - - - bout6 pf6 21 136 dvcc - - - - - - - - - - - bout7 pf7 22 135 dvss - - - - - - - - - - - dckout pg4 23 134 p067 pwm2m1 an15 - - - - - - - - - vsync pg5 24 133 p066 pwm2p1 an14 - - - - - - - - - hsync pg6 25 132 p065 pwm1m1 an13 - - - - - - - - - deout pg7 26 131 p064 pwm1p1 an12 - - - - - ppg0 tin0_2 sin2_1 d0 p000 27 130 p063 pwm2m0 an11 - - - - - ppg1 tin1_2 sot2_1 d1 p001 28 129 p062 pwm2p0 an10 - - - - - ppg2 tin2_2 sck2_1 d2 p002 29 128 p061 pwm1m0 an9 - - - - - ppg3 tin3_2 sin3_1 d3 p003 30 127 p060 pwm1p0 an8 - - - - - ppg4 tot0_2 sot3_1 d4 p004 31 126 dvcc - - - - - - - ppg5 tot1_2 sck3_1 d5 p005 32 125 dvss - - - - - - - ppg6 tot2_2 - d6 p006 33 124 c_1 - - - - - - - ppg7 tot3_2 - d7 p007 34 123 vss - - - - - - - - - - d8 p010 35 122 vcc5 - - - - - - - - - - - - vss 36 121 p107 sgo4_1 an7 - - - ppg5_1 - - - - - - vcc3 37 120 p106 sga4_1 an6 - - - ppg4_1 - - - rout0 d9 p011 38 119 p105 sck5_1 an5 tot1_1 - - ppg3_1 - - - rout1 d10 p012 39 118 p104 sot5_1 an4 tot0_1 - - ppg2_1 - - - gout0 d11 p013 40 117 p103 sin5_1 an3 tin3_1 - - ppg1_1 - - - gout1 d12 p014 41 116 p102 sck4_1 an2 tin2_1 - - ppg10 - - - bout0 d13 p015 42 115 p101 sot4_1 an1 tin1_1 - - ppg9 - - - bout1 d14 p016 43 114 p100 sin4_1 an0 tin0_1 - - ppg8 - - - - d15 p017 44 113 avss5/avrl5 - - - - - - - - - - wex p020 45 112 avrh5 - - - - - - - - - - cs0x p021 46 111 avcc5 - - - - - - - - - - cs1x p022 47 110 p125 ocu3 - - icu0 - ppg10_2 - - - - rex p023 48 109 p124 ocu2 - - icu5_2 - ppg9_2 - - - - - p024 49 108 p123 ocu1 - - - - ppg8_2 - - - - - p025 50 107 p096 rx0 - int9 - - - - - - - a00 p026 51 106 p095 tx0 - - - - ppg10_1 - - - - - - vss 52 105 vcc5 - - - - - - 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 vcc3 p027 p030 p031 p032 p033 p034 p035 p036 p037 p040 p041 p042 p043 p044 p045 p046 p047 vcc3 vss c_2 p050 p051 p052 p053 p054 p055 p056 p057 vss x1 x0 md1 md0 rstx vss vcc5 p126 p127 p130 p131 p132 p133 p134 nmix p091 p092 p093 p110 p111 debugif vss - a01 a02 a03 a04 a05 a06 a07 a08 a09 a10 a11 a12 a13 a14 a15 a16 a17 - - - a18 a19 a20 a21 a22 a23 a24 rdy - - - - - - - - trg0 - - trg1 - trg5 trg2 - sga0 sgo0 sga1 tx1 rx1 - - - - - - - - - - - - - - - - - - - - - - - - - - spi_do spi_di spi_sck spi_xcs - - - - - - - - - sin0 sot0 sck0 - - ppg11_1 ppg1_3 - sin2 sck2 sot2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - sin1 sot1 sck1 - - int12 int13 int14 - int10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - int1 - int0 int4 int2 int3 int5 - tot2_1 tot3_1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - icu1 icu2 icu3 icu4 icu5 - icu2_1 icu0_1 icu3_1 - - - - - - - - - - - - - - - - - - tioa0 tioa1 tiob0 tiob1 - - ppg6_1 ppg7_1 ppg8_1 ppg1_2 ppg2_2 - - fr+gdc top view lqfp-208 / hqfp-208 (dual clock product) (dual clock product) document number: 002- 04727 rev. *b page 13 of 174 mb91590 series 2.3 pin assignment (mb91f59a/b single clock product ) (top view) vss avcc3 avss3 vin refout avr3 avss3 avcc3 pg0/dckin/cmdtrg pg3/csout pg2/hsin pg1/vsin ph3/cclk pc7/bin7 pc6/bin6 pc5/bin5 pc4/bin4 pc3/bin3 pc2/bin2 vcc3 vss pb7/gin7 pb6/gin6 pb5/gin5 pb4/gin4 pb3/gin3/vin7 pb2/gin2/vin6 pa7/rin7/vin5 pa6/rin6/vin4 pa5/rin5/vin3 pa4/rin4/vin2 pa3/rin3/vin1 pa2/rin2/vin0 vcc3 vss vcc5 p136 p137 vss md2 p122/ocu0/sck5/tot3/ppg7_2 p121/frck0/sot5/int7/tot2/ppg6_2 p120/frck1/sin5/int6/tot1/ppg5_2 p117/sgo3/sck4/trg4/tot0/frck2 p116/sga3/sot4/tin3/frck3 p115/sgo2/sin4/tin2/frck4 p114/sga2/sck3/trg3/tin1/icu5_1/frck7 p097/wot/sot3/int8/tin0/icu4_1/ppg0_1 p094/sgo1/sin3/int15/icu1_1/ppg9_1/tin9_1 p113/rx2/int11/ppg4_2/tin7 p112/tx2/ppg3_2/tot10_1 p090/adtg/ppg0_2/tin7_1 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 vcc3 1 156 dvcc pd2/rout2 2 155 d vss pd3/rout3 3 154 p087/pwm2m5/an31/icu4_2/ppg23 pd4/rout4 4 153 p086/pwm2p5/an30/icu3_2/ppg22 pd5/rout5 5 152 p085/pwm1m5/an29/icu2_2/ppg21/udcain2 pd6/rout6 6 151 p084/pwm1p5/an28/icu1_2/ppg20/udcbin2 pd7/rout7 7 150 p083/pwm2m4/an27/icu0_2/ppg19/udczin2 pe2/gout2 8 149 p082/pwm2p4/an26/sck6/ppg18/udczin0_1 pe3/gout3 9 148 p081/pwm1m4/an25/sot6/ppg17/udcbin0_1 pe4/gout4 10 147 p080/pwm1p4/an24/sin6/ppg16/udcain0_1 pe5/gout5 11 146 dvcc pe6/gout6 12 145 d vss pe7/gout7 13 144 p077/pwm2m3/an23/sck7_1/ppg15_1/icu6 pf2/bout2 14 143 p076/pwm2p3/an22/sot7_1/ppg14_1/icu7 pf3/bout3 15 142 p075/pwm1m3/an21/sin7_1/ppg13_1/icu8 pf4/bout4 16 141 p074/pwm1p3/an20/ppg12_1/sck8/icu9 pf5/bout5 17 140 p073/pwm2m2/an19/sot8/icu10 vcc3 18 139 p072/pwm2p2/an18/sin8/icu11 vss 19 138 p071/pwm1m2/an17/sck9 c_3 20 137 p070/pwm1p2/an16/sot9 pf6/bout6 21 136 dvcc pf7/bout7 22 135 d vss pg4/dckout 23 134 p067/pwm2m1/an15/udcain0/sin9 pg5 /vsyn c 24 133 p066/pwm2p1/an14/udcbin0 pg6/hsync 25 132 p065/pwm1m1/an13/udczin0 pg7/deout 26 131 p064/pwm1p1/an12/udcain1 p000/d0/sin2_1/tin0_2/ppg0 27 130 p063/pwm2m0/an11/udcbin1 p001/d1/sot2_1/tin1_2/ppg1 28 129 p062/pwm2p0/an10/udczin1/sck10 p002/d2/sck2_1/tin2_2/ppg2 29 128 p061/pwm1m0/an9/sot10 p003/d3/sin3_1/tin3_2/ppg3 30 127 p060/pwm1p0/an8/sin10 p004/d4/sot3_1/tot0_2/ppg4 31 126 dvcc p005/d5/sck3_1/tot1_2/ppg5 32 125 d vss p006/d6/tot2_2/ppg6 33 124 c_1 p007/d7/tot3_2/ppg7 34 123 vss p010/d8 35 122 vcc5 vss 36 121 p107/sgo4_1/an7/ppg5_1/tot7_1/icu11_1 vcc3 37 120 p106/sga4_1/an6/ppg4_1/tin10_1/icu10_1 p011/d9/rout0 38 119 p105/sck5_1/an5/tot1_1/ppg3_1/icu9_1 p012/d10/rout1 39 118 p104/sot5_1/an4/tot0_1/ppg2_1/icu8_1 p013/d11/gout0 40 117 p103/sin5_1/an3/tin3_1/ppg1_1/icu7_1 p014/d12/gout1 41 116 p102/sck4_1/an2/tin2_1/ppg10/icu6_1 p015/d13/bout0 42 115 p101/sot4_1/an1/tin1_1/ppg9 p016/d14/bout1 43 114 p100/sin4_1/an0/tin0_1/ppg8 p017/d15 44 113 avss5 /avr l 5 p020/wex 45 112 avr h 5 p021/cs0x 46 111 avc c 5 p022/cs1x 47 110 p125/ocu3/icu0/ppg10_2/tin10/sck11 p023/rex 48 109 p124/ocu2/icu5_2/ppg9_2/tin9/sot11 p024 49 108 p123/ocu1/ppg8_2/tin8/sin11 p025 50 107 p096/rx0/int9 p026/a00 51 106 p095/tx0/ppg10_1 vss 52 105 vcc5 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 vcc3 p027/a01 p030/a02 p031/a03 p032/a04 p033/a05 p034/a06 p035/a07 p036/a08 p037/a09/qspi_sio0 p040/a10/qspi_sio1 p041/a11/qspi_sio2 p042/a12/qspi_sio3 p043/a13/qspi_cs0 p044/a14/qspi_cs1 p045/a15/qspi_cs2 p046/a16/qspi_cs3 p047/a17/qspi_clk vcc3 vss c_2 p050/a18 p051/a19 p052/a20 p053/a21/spi_do p054/a22/spi_di p055/a23/spi_sck p056/a24/spi_xcs p057/rdy vss x1 x0 md1 md0 rstx vss vcc5 p126/trg0/sin0/int1 p127/sot0 p130/sck0/int0/icu1/tioa0 p131/trg1/sin1/int4/icu2/tioa1/tot7 p132/sot1/int2/icu3/tiob0/tot8 p133/trg5/ppg11_1/sck1/int3/icu4/tiob1/tot9 p134/trg2/ppg1_3/int5/icu5/tot10 nmix p091/sga0/sin2/int12/tot2_1/icu2_1/ppg6_1 p092/sgo0/sck2/int13/tot3_1/icu0_1/ppg7_1 p093/sga1/sot2/int14/icu3_1/ppg8_1/tin8_1 p110/tx1/ppg1_2/frck5/tot8_1 p111/rx1/int10/ppg2_2/frck6/tot9_1 debugif vss document number: 002- 04727 rev. *b page 14 of 174 mb91590 series 2.4 pin assignment (mb91f59a/b dual clock product ) (top view) vss avcc3 avss3 vin refout avr3 avss3 avcc3 pg0/dckin/cmdtrg pg3/csout pg2/hsin pg1/vsin ph3/cclk pc7/bin7 pc6/bin6 pc5/bin5 pc4/bin4 pc3/bin3 pc2/bin2 vcc3 vss pb7/gin7 pb6/gin6 pb5/gin5 pb4/gin4 pb3/gin3/vin7 pb2/gin2/vin6 pa7/rin7/vin5 pa6/rin6/vin4 pa5/rin5/vin3 pa4/rin4/vin2 pa3/rin3/vin1 pa2/rin2/vin0 vcc3 vss vcc5 x1a x0a vss md2 p122/ocu0/sck5/tot3/ppg7_2 p121/frck0/sot5/int7/tot2/ppg6_2 p120/frck1/sin5/int6/tot1/ppg5_2 p117/sgo3/sck4/trg4/tot0/frck2 p116/sga3/sot4/tin3/frck3 p115/sgo2/sin4/tin2/frck4 p114/sga2/sck3/trg3/tin1/icu5_1/frck7 p097/wot/sot3/int8/tin0/icu4_1/ppg0_1 p094/sgo1/sin3/int15/icu1_1/ppg9_1/tin9_1 p113/rx2/int11/ppg4_2/tin7 p112/tx2/ppg3_2/tot10_1 p090/adtg/ppg0_2/tin7_1 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 vcc3 1 156 dvcc pd2/rout2 2 155 d vss pd3/rout3 3 154 p087/pwm2m5/an31/icu4_2/ppg23 pd4/rout4 4 153 p086/pwm2p5/an30/icu3_2/ppg22 pd5/rout5 5 152 p085/pwm1m5/an29/icu2_2/ppg21/udcain2 pd6/rout6 6 151 p084/pwm1p5/an28/icu1_2/ppg20/udcbin2 pd7/rout7 7 150 p083/pwm2m4/an27/icu0_2/ppg19/udczin2 pe2/gout2 8 149 p082/pwm2p4/an26/sck6/ppg18/udczin0_1 pe3/gout3 9 148 p081/pwm1m4/an25/sot6/ppg17/udcbin0_1 pe4/gout4 10 147 p080/pwm1p4/an24/sin6/ppg16/udcain0_1 pe5/gout5 11 146 dvcc pe6/gout6 12 145 d vss pe7/gout7 13 144 p077/pwm2m3/an23/sck7_1/ppg15_1/icu6 pf2/bout2 14 143 p076/pwm2p3/an22/sot7_1/ppg14_1/icu7 pf3/bout3 15 142 p075/pwm1m3/an21/sin7_1/ppg13_1/icu8 pf4/bout4 16 141 p074/pwm1p3/an20/ppg12_1/sck8/icu9 pf5/bout5 17 140 p073/pwm2m2/an19/sot8/icu10 vcc3 18 139 p072/pwm2p2/an18/sin8/icu11 vss 19 138 p071/pwm1m2/an17/sck9 c_3 20 137 p070/pwm1p2/an16/sot9 pf6/bout6 21 136 dvcc pf7/bout7 22 135 d vss pg4/dckout 23 134 p067/pwm2m1/an15/udcain0/sin9 pg5 /vsyn c 24 133 p066/pwm2p1/an14/udcbin0 pg6/hsync 25 132 p065/pwm1m1/an13/udczin0 pg7/deout 26 131 p064/pwm1p1/an12/udcain1 p000/d0/sin2_1/tin0_2/ppg0 27 130 p063/pwm2m0/an11/udcbin1 p001/d1/sot2_1/tin1_2/ppg1 28 129 p062/pwm2p0/an10/udczin1/sck10 p002/d2/sck2_1/tin2_2/ppg2 29 128 p061/pwm1m0/an9/sot10 p003/d3/sin3_1/tin3_2/ppg3 30 127 p060/pwm1p0/an8/sin10 p004/d4/sot3_1/tot0_2/ppg4 31 126 dvcc p005/d5/sck3_1/tot1_2/ppg5 32 125 d vss p006/d6/tot2_2/ppg6 33 124 c_1 p007/d7/tot3_2/ppg7 34 123 vss p010/d8 35 122 vcc5 vss 36 121 p107/sgo4_1/an7/ppg5_1/tot7_1/icu11_1 vcc3 37 120 p106/sga4_1/an6/ppg4_1/tin10_1/icu10_1 p011/d9/rout0 38 119 p105/sck5_1/an5/tot1_1/ppg3_1/icu9_1 p012/d10/rout1 39 118 p104/sot5_1/an4/tot0_1/ppg2_1/icu8_1 p013/d11/gout0 40 117 p103/sin5_1/an3/tin3_1/ppg1_1/icu7_1 p014/d12/gout1 41 116 p102/sck4_1/an2/tin2_1/ppg10/icu6_1 p015/d13/bout0 42 115 p101/sot4_1/an1/tin1_1/ppg9 p016/d14/bout1 43 114 p100/sin4_1/an0/tin0_1/ppg8 p017/d15 44 113 avss5 /avr l 5 p020/wex 45 112 avr h 5 p021/cs0x 46 111 avc c 5 p022/cs1x 47 110 p125/ocu3/icu0/ppg10_2/tin10/sck11 p023/rex 48 109 p124/ocu2/icu5_2/ppg9_2/tin9/sot11 p024 49 108 p123/ocu1/ppg8_2/tin8/sin11 p025 50 107 p096/rx0/int9 p026/a00 51 106 p095/tx0/ppg10_1 vss 52 105 vcc5 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 vcc3 p027/a01 p030/a02 p031/a03 p032/a04 p033/a05 p034/a06 p035/a07 p036/a08 p037/a09/qspi_sio0 p040/a10/qspi_sio1 p041/a11/qspi_sio2 p042/a12/qspi_sio3 p043/a13/qspi_cs0 p044/a14/qspi_cs1 p045/a15/qspi_cs2 p046/a16/qspi_cs3 p047/a17/qspi_clk vcc3 vss c_2 p050/a18 p051/a19 p052/a20 p053/a21/spi_do p054/a22/spi_di p055/a23/spi_sck p056/a24/spi_xcs p057/rdy vss x1 x0 md1 md0 rstx vss vcc5 p126/trg0/sin0/int1 p127/sot0 p130/sck0/int0/icu1/tioa0 p131/trg1/sin1/int4/icu2/tioa1/tot7 p132/sot1/int2/icu3/tiob0/tot8 p133/trg5/ppg11_1/sck1/int3/icu4/tiob1/tot9 p134/trg2/ppg1_3/int5/icu5/tot10 nmix p091/sga0/sin2/int12/tot2_1/icu2_1/ppg6_1 p092/sgo0/sck2/int13/tot3_1/icu0_1/ppg7_1 p093/sga1/sot2/int14/icu3_1/ppg8_1/tin8_1 p110/tx1/ppg1_2/frck5/tot8_1 p111/rx1/int10/ppg2_2/frck6/tot9_1 debugif vss document number: 002- 04727 rev. *b page 15 of 174 mb91590 series 2.5 pin assignment (bga product ) (top view) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 a 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 a b 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 2 1 b c 7 5 1 4 4 1 4 5 1 4 6 1 4 7 1 4 8 1 4 9 1 5 0 1 5 1 1 5 2 1 5 3 1 5 4 1 5 5 1 5 6 1 5 7 1 5 8 1 5 9 1 6 0 9 5 2 2 c d 7 4 1 4 3 2 0 4 2 0 5 2 0 6 2 0 7 2 0 8 2 0 9 2 1 0 2 1 1 2 1 2 2 1 3 2 1 4 2 1 5 2 1 6 2 1 7 2 1 8 1 6 1 9 6 2 3 d e 7 3 1 4 2 2 0 3 2 5 6 2 1 9 1 6 2 9 7 2 4 e f 7 2 1 4 1 20 2 2 5 5 2 2 0 1 6 3 9 8 2 5 f g 7 1 1 4 0 2 0 1 2 5 4 2 5 7 2 5 8 2 5 9 2 6 0 2 6 1 2 6 2 2 6 3 2 6 4 2 2 1 1 6 4 9 9 2 6 g h 7 0 1 3 9 2 0 0 2 5 3 2 8 4 2 8 5 2 8 6 2 8 7 2 8 8 2 8 9 2 9 0 2 6 5 22 2 1 6 5 1 0 0 2 7 h j 6 9 1 3 8 1 9 9 2 5 2 2 8 3 3 0 4 3 0 5 3 0 6 3 0 7 30 8 2 9 1 2 6 6 2 2 3 1 6 6 1 0 1 2 8 j k 6 8 1 3 7 1 9 8 2 5 1 2 8 2 3 0 3 3 1 6 3 1 7 3 1 8 3 0 9 2 9 2 2 6 7 2 2 4 1 6 7 1 0 2 2 9 k l 6 7 1 3 6 1 9 7 2 5 0 2 8 1 3 0 2 3 1 5 3 2 0 3 1 9 3 1 0 2 9 3 2 6 8 2 2 5 1 6 8 1 0 3 3 0 l m 6 6 1 3 5 1 9 6 2 4 9 2 8 0 3 0 1 3 1 4 3 1 3 3 1 2 3 1 1 2 9 4 2 6 9 2 2 6 1 6 9 1 0 4 3 1 m n 6 5 1 3 4 1 9 5 2 4 8 2 7 9 3 0 0 2 9 9 2 9 8 2 9 7 2 9 6 2 9 5 2 7 0 2 2 7 1 7 0 1 0 5 3 2 n p 6 4 1 3 3 1 9 4 2 4 7 2 7 8 2 7 7 2 7 6 2 7 5 2 7 4 2 7 3 2 7 2 2 7 1 2 2 8 1 7 1 1 0 6 3 3 p r 6 3 1 3 2 1 9 3 2 4 6 2 2 9 1 7 2 1 0 7 3 4 r t 6 2 1 3 1 1 9 2 2 4 5 2 3 0 1 7 3 1 0 8 3 5 t u 6 1 1 3 0 1 9 1 2 4 4 2 4 3 2 4 2 2 4 1 2 4 0 2 3 9 2 3 8 2 3 7 2 3 6 2 3 5 2 3 4 2 3 3 2 3 2 2 3 1 1 7 4 1 0 9 3 6 u v 6 0 1 2 9 1 9 0 1 8 9 1 8 8 1 8 7 1 8 6 1 8 5 1 8 4 1 8 3 1 8 2 1 8 1 1 8 0 1 7 9 1 7 8 1 7 7 1 7 6 1 7 5 1 1 0 3 7 v w 5 9 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 11 1 3 8 w y 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 y 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 document number: 002- 04727 rev. *b page 16 of 174 mb91590 series 3. pin description 3.1 pin description of lqfp - 208/teqfp - 208 pin no . pin name polarity i/o circuit types *1 function *2 84 x0 ? l main clock oscillation input pin 83 x1 ? l main clock oscillation output pin 171 (dual clock product) x0a ? n sub clock oscillation input pin 172 (dual clock product) x1a ? n sub clock oscillation output pin 171 (single clock product) p137 ? a general - purpose i/o port 172 (single clock product) p136 ? a general - purpose i/o port 97 nmix n f1 non - masking interrupt input pin 87 rstx n f1 external reset input pin 86 md0 ? p mode pin 0 85 md1 ? p mode pin 1 169 md2 ? f2 mode pin 2 27 p000 ? o general - purpose i/o port (3v pin) d0 ? external bus data bit0 i/o pin sin2_1 ? lin - uart ch.2 serial data input pin (1) tin0_2 ? reload timer ch.0 event input pin (2) ppg0 ? ppg ch.0 output pin 28 p001 ? o general - purpose i/o port (3v pin) d1 ? external bus data bit1 i/o pin sot2_1 ? lin - uart ch.2 serial data output pin (1) tin1_2 ? reload timer ch.1 event input pin (2) ppg1 ? ppg ch.1 output pin 29 p002 ? o general - purpose i/o port (3v pin) d2 ? external bus data bit2 i/o pin sck2_1 ? lin - uart ch.2 clock i/o pin (1) tin2_2 ? reload timer ch.2 event input pin (2) ppg2 ? ppg ch.2 output pin 30 p003 ? o general - purpose i/o port (3v pin) d3 ? external bus data bit3 i/o pin sin3_1 ? lin - uart ch.3 serial data input pin (1) tin3_2 ? reload timer ch.3 event input pin (2) ppg3 ? ppg ch.3 output pin 31 p004 ? o general - purpose i/o port (3v pin) d4 ? external bus data bit4 i/o pin sot3_1 ? lin - uart ch.3 serial data output pin (1) tot0_2 ? reload timer ch.0 output pin (2) ppg4 ? ppg ch.4 output pin document number: 002- 04727 rev. *b page 17 of 174 mb91590 series pin no . pin name polarity i/o circuit types *1 function *2 32 p005 ? o general - purpose i/o port (3v pin) d5 ? external bus data bit5 i/o pin sck3_1 ? lin - uart ch.3 clock i/o pin (1) tot1_2 ? reload timer ch.1 output pin (2) ppg5 ? ppg ch.5 output pin 33 p006 ? o general - purpose i/o port (3v pin) d6 ? external bus data bit6 i/o pin tot2_2 ? reload timer ch.2 output pin (2) ppg6 ? ppg ch.6 output pin 34 p007 ? o general - purpose i/o port (3v pin) d7 ? external bus data bit7 i/o pin tot3_2 ? reload timer ch.3 output pin (2) ppg7 ? ppg ch.7 output pin 35 p010 ? o general - purpose i/o port (3v pin) d8 ? external bus data bit8 i/o pin 38 p011 ? o general - purpose i/o port (3v pin) d9 ? external bus data bit9 i/o pin rout0 ? display digital r0 output pin 39 p012 ? o general - purpose i/o port (3v pin) d10 ? external bus data bit10 i/o pin rout1 ? display digital r1 output pin 40 p013 ? o general - purpose i/o port (3v pin) d11 ? external bus data bit11 i/o pin gout0 ? display digital g0 output pin 41 p014 ? o general - purpose i/o port (3v pin) d12 ? external bus data bit12 i/o pin gout1 ? display digital g1 output pin 42 p015 ? o general - purpose i/o port (3v pin) d13 ? external bus data bit13 i/o pin bout0 ? display digital b0 output pin 43 p016 ? o general - purpose i/o port (3v pin) d14 ? external bus data bit14 i/o pin bout1 ? display digital b1 output pin 44 p017 ? o general - purpose i/o port (3v pin) d15 ? external bus data bit15 i/o pin 45 p020 ? o general - purpose i/o port (3v pin) wex ? external bus write enable output pin 46 p021 ? o general - purpose i/o port (3v pin) cs0x ? external bus chip select 0 output pin 47 p022 ? o general - purpose i/o port (3v pin) cs1x ? external bus chip select 1 output pin 48 p023 ? o general - purpose i/o port (3v pin) rex ? external bus read enable output pin 49 p024 ? o general - purpose i/o port (3v pin) 50 p025 ? o general - purpose i/o port (3v pin) 51 p026 ? o general - purpose i/o port (3v pin) a00 ? external bus address bit0 output pin 54 p027 ? o general - purpose i/o port (3v pin) a01 ? external bus address bit1 output pin document number: 002- 04727 rev. *b page 18 of 174 mb91590 series pin no . pin name polarity i/o circuit types *1 function *2 55 p030 ? o general - purpose i/o port (3v pin) a02 ? external bus address bit2 output pin 56 p031 ? o general - purpose i/o port (3v pin) a03 ? external bus address bit3 output pin 57 p032 ? o general - purpose i/o port (3v pin) a04 ? external bus address bit4 output pin 58 p033 ? o general - purpose i/o port (3v pin) a05 ? external bus address bit5 output pin 59 p034 ? o general - purpose i/o port (3v pin) a06 ? external bus address bit6 output pin 60 p035 ? o general - purpose i/o port (3v pin) a07 ? external bus address bit7 output pin 61 p036 ? o general - purpose i/o port (3v pin) a08 ? external bus address bit8 output pin 62 p037 ? o general - purpose i/o port (3v pin) a09 ? external bus address bit9 output pin qspi_sio0 ? hs_spi sdata0 i/o pin(mb91f59a/b only) 63 p040 ? o general - purpose i/o port (3v pin) a10 ? external bus address bit10 output pin qspi_sio1 ? hs_spi sdata1 i/o pin(mb91f59a/b only) 64 p041 ? o general - purpose i/o port (3v pin) a11 ? external bus address bit11 output pin qspi_sio2 ? hs_spi sdata2 i/o pin(mb91f59a/b only) 65 p042 ? o general - purpose i/o port (3v pin) a12 ? external bus address bit12 output pin qspi_sio3 ? hs_spi sdata3 i/o pin(mb91f59a/b only) 66 p043 ? o general - purpose i/o port (3v pin) a13 ? external bus address bit13 output pin qspi_cs0 ? hs_spi ssel0 output pin(mb91f59a/b only) 67 p044 ? o general - purpose i/o port (3v pin) a14 ? external bus address bit14 output pin qspi_cs1 ? hs_spi ssel1 output pin(mb91f59a/b only) 68 p045 ? o general - purpose i/o port (3v pin) a15 ? external bus address bit15 output pin qspi_cs2 ? hs_spi ssel2 output pin(mb91f59a/b only) 69 p046 ? o general - purpose i/o port (3v pin) a16 ? external bus address bit16 output pin qspi_cs3 ? hs_spi ssel3 output pin (mb91f59a/b only) 70 p047 ? o general - purpose i/o port (3v pin) a17 ? external bus address bit17 output pin qspi_clk ? hs_spi sclk output pin (mb91f59a/b only) 74 p050 ? o general - purpose i/o port (3v pin) a18 ? external bus address bit18 output pin 75 p051 ? o general - purpose i/o port(3v pin) a19 ? external bus address bit19 output pin 76 p052 ? o general - purpose i/o port(3v pin) a20 ? external bus address bit20 output pin document number: 002- 04727 rev. *b page 19 of 174 mb91590 series pin no . pin name polarity i/o circuit types *1 function *2 77 p053 ? o general - purpose i/o port(3v pin) a21 ? external bus address bit21 output pin spi_do ? spi data output pin 78 p054 ? o general - purpose i/o port (3v pin) a22 ? external bus address bit22 output pin spi_di ? spi data input pin 79 p055 ? o general - purpose i/o port (3v pin) a23 ? external bus address bit23 output pin spi_sck ? spi clock output pin 80 p056 ? o general - purpose i/o port (3v pin) a24 ? external bus address bit24 output pin spi_xcs ? spi chip select output pin 81 p057 ? o general - purpose i/o port (3v pin) rdy ? external bus wait input pin 127 p060 ? e general - purpose i/o port pwm1p0 ? smc ch.0 output pin an8 ? adc analog 8 input pin sin10 ? multi - function serial ch.10 serial data input pin (mb91f59a/b only) 128 p061 ? e general - purpose i/o port pwm1m0 ? smc ch.0 output pin an9 ? adc analog 9 input pin sot10 ? multi - function serial ch.10 serial data output pin (mb91f59a/b only) 129 p062 ? e general - purpose i/o port pwm2p0 ? smc ch.0 output pin an10 ? adc analog 10 input pin udczin1 ? up/down counter ch.1 zin input pin (mb91f59a/b only) sck10 ? multi - function serial ch.10 clock i/o pin (mb91f59a/b only) 130 p063 ? e general - purpose i/o port pwm2m0 ? smc ch.0 output pin an11 ? adc analog 11 input pin udcbin1 ? up/down counter ch.1 bin input pin (mb91f59a/b only) 131 p064 ? e general - purpose i/o port pwm1p1 ? smc ch.1 output pin an12 ? adc analog 12 input pin udcain1 ? up/down counter ch.1 ain input pin (mb91f59a/b only) 132 p065 ? e general - purpose i/o port pwm1m1 ? smc ch.1 output pin an13 ? adc analog 13 input pin udczin0 ? up/down counter ch.0 zin input pin (mb91f59a/b only) 133 p066 ? e general - purpose i/o port pwm2p1 ? smc ch.1 output pin an14 ? adc analog 14 input pin udcbin0 ? up/down counter ch.0 bin input pin (mb91f59a/b only) document number: 002- 04727 rev. *b page 20 of 174 mb91590 series pin no . pin name polarity i/o circuit types *1 function *2 134 p067 ? e general - purpose i/o port pwm2m1 ? smc ch.1 output pin an15 ? adc analog 15 input pin udcain0 ? up/down counter ch.0 ain input pin (mb91f59a/b only) sin9 ? multi - function serial ch.9 serial data input pin (mb91f59a/b only) 137 p070 ? e general - purpose i/o port pwm1p2 ? smc ch.2 output pin an16 ? adc analog 16 input pin sot9 ? multi - function serial ch.9 serial data output pin (mb91f59a/b only) 138 p071 ? e general - purpose i/o port pwm1m2 ? smc ch.2 output pin an17 ? adc analog 17 input pin sck9 ? multi - function serial ch.9 clock i/o pin (mb91f59a/b only) 139 p072 ? e general - purpose i/o port pwm2p2 ? smc ch.2 output pin an18 ? adc analog 18 input pin sin8 ? multi - function serial ch.8 serial data input pin (mb91f59a/b only) icu11 ? input capture ch.11 input pin (mb91f59a/b only) 140 p073 ? e general - purpose i/o port pwm2m2 ? smc ch.2 output pin an19 ? adc analog 19 input pin sot8 ? multi - function serial ch.8 serial data output pin (mb91f59a/b only) icu10 ? input capture ch.10 input pin (mb91f59a/b only) 141 p074 ? e general - purpose i/o port pwm1p3 ? smc ch.3 output pin an20 ? adc analog 20 input pin ppg12_1 ? ppg ch.12 output pin (1) sck8 ? multi - function serial ch.8 clock i/o pin (mb91f59a/b only) icu9 ? input capture ch.9 input pin (mb91f59a/b only) 142 p075 ? e general - purpose i/o port pwm1m3 ? smc ch.3 output pin an21 ? adc analog 21 input pin sin7_1 ? lin - uart ch.7 serial data input pin ppg13_1 ? ppg ch.13 output pin (1) icu8 ? input capture ch.8 input pin (mb91f59a/b only) 143 p076 ? e general - purpose i/o port pwm2p3 ? smc ch.3 output pin an22 ? adc analog 22 input pin sot7_1 ? lin - uart ch.7 serial data output pin ppg14_1 ? ppg ch.14 output pin (1) icu7 ? input capture ch.7 input pin (mb91f59a/b only) document number: 002- 04727 rev. *b page 21 of 174 mb91590 series pin no . pin name polarity i/o circuit types *1 function *2 144 p077 ? e general - purpose i/o port pwm2m3 ? smc ch.3 output pin an23 ? adc analog 23 input pin sck7_1 ? lin - uart ch.7 clock i/o pin ppg15_1 ? ppg ch.15 output pin (1) icu6 ? input capture ch.6 input pin (mb91f59a/b only) 147 p080 ? e general - purpose i/o port pwm1p4 ? smc ch.4 output pin an24 ? adc analog 24 input pin sin6 ? lin - uart ch.6 serial data input pin ppg16 ? ppg ch.16 output pin udcain0_1 ? up/down counter ch.0 ain input pin (1) (mb91f59a/b only) 148 p081 ? e general - purpose i/o port pwm1m4 ? smc ch.4 output pin an25 ? adc analog 25 input pin sot6 ? lin - uart ch.6 serial data output pin ppg17 ? ppg ch.17 output pin udcbin0_1 ? up/down counter ch.0 bin input pin (1) (mb91f59a/b only) 149 p082 ? e general - purpose i/o port pwm2p4 ? smc ch.4 output pin an26 ? adc analog 26 input pin sck6 ? lin - uart ch.6 clock i/o pin ppg18 ? ppg ch.18 output pin udczin0_1 ? up/down counter ch.0 zin input pin (1) (mb91f59a/b only) 150 p083 ? e general - purpose i/o port pwm2m4 ? smc ch.4 output pin an27 ? adc analog 27 input pin icu0_2 ? input capture ch.0 input pin (2) ppg19 ? ppg ch.19 output pin udczin2 ? up/down counter ch.2 zin input pin (mb91f59a/b only) 151 p084 ? e general - purpose i/o port pwm1p5 ? smc ch.5 output pin an28 ? adc analog 28 input pin icu1_2 ? input capture ch.1 input pin (2) ppg20 ? ppg ch.20 output pin udcbin2 ? up/down counter ch.2 bin input pin (mb91f59a/b only) 152 p085 ? e general - purpose i/o port pwm1m5 ? smc ch.5 output pin an29 ? adc analog 29 input pin icu2_2 ? input capture ch.2 input pin (2) ppg21 ? ppg ch.21 output pin udcain2 ? up/down counter ch.2 ain input pin (mb91f59a/b only) 153 p086 ? e general - purpose i/o port pwm2p5 ? smc ch.5 output pin an30 ? adc analog 30 input pin icu3_2 ? input capture ch.3 input pin (2) ppg22 ? ppg ch.22 output pin document number: 002- 04727 rev. *b page 22 of 174 mb91590 series pin no . pin name polarity i/o circuit types *1 function *2 154 p087 ? e general - purpose i/o port pwm2m5 ? smc ch.5 output pin an31 ? adc analog 31 input pin icu4_2 ? input capture ch.4 input pin (2) ppg23 ? ppg ch.23 output pin 157 p090 ? a general - purpose i/o port adtg ? a/d convertor external trigger input pin ppg0_2 ? ppg ch.0 output pin (2) tin7_1 ? reload timer ch.7 event input pin (1) (mb91f59a/b only) 98 p091 ? c general - purpose i/o port sga0 ? sound generator ch.0 sga output pin sin2 ? lin - uart ch.2 serial data input pin int12 ? int12 external interrupt input pin tot2_1 ? reload timer ch.2 output pin (1) icu2_1 ? input capture ch.2 input pin (1) ppg6_1 ? ppg ch.6 output pin (1) 99 p092 ? c general - purpose i/o port sgo0 ? sound generator ch.0 sgo output pin sck2 ? lin - uart ch.2 clock i/o pin int13 ? int13 external interrupt input pin tot3_1 ? reload timer ch.3 output pin (1) icu0_1 ? input capture ch.0 input pin (1) ppg7_1 ? ppg ch.7 output pin (1) 100 p093 ? c general - purpose i/o port sga1 ? sound generator ch.1 sga output pin sot2 ? lin - uart ch.2 serial data output pin int14 ? int14 external interrupt input pin icu3_1 ? input capture ch.3 input pin (1) ppg8_1 ? ppg ch.8 output pin (1) tin8_1 ? reload timer ch.8 event input pin (1) (mb91f59a/b only) 160 p094 ? c general - purpose i/o port sgo1 ? sound generator ch.1 sgo output pin sin3 ? lin - uart ch.3 serial data input pin int15 ? int15 external interrupt input pin icu1_1 ? input capture ch.1 input pin (1) ppg9_1 ? ppg ch.9 output pin (1) tin9_1 ? reload timer ch.9 event input pin (1) (mb91f59a/b only) 106 p095 ? a general - purpose i/o port tx0 ? can transmission data0 output pin ppg10_1 ? ppg ch.10 output pin (1) 107 p096 ? a general - purpose i/o port rx0 ? can reception data0 input pin int9 ? int9 external interrupt input pin document number: 002- 04727 rev. *b page 23 of 174 mb91590 series pin no . pin name polarity i/o circuit types *1 function *2 161 p097 ? c general - purpose i/o port wot ? rtc overflow output pin sot3 ? lin - uart ch.3 serial data output pin int8 ? int8 external interrupt input pin tin0 ? reload timer ch.0 event input pin icu4_1 ? input capture ch.4 input pin (1) ppg0_1 ? ppg ch.0 output pin (1) 114 p100 ? c general - purpose i/o port sin4_1 ? lin - uart ch.4 serial data input pin (1) an0 ? adc analog 0 input pin tin0_1 ? reload timer ch.0 event input pin (1) ppg8 ? ppg ch.8 output pin 115 p101 ? c general - purpose i/o port sot4_1 ? lin - uart ch.4 serial data output pin (1) an1 ? adc analog 1 input pin tin1_1 ? reload timer ch.1 event input pin (1) ppg9 ? ppg ch.9 output pin 116 p102 ? c general - purpose i/o port sck4_1 ? lin - uart ch.4 clock i/o pin (1) an2 ? adc analog 2 input pin tin2_1 ? reload timer ch.2 event input pin (1) ppg10 ? ppg ch.10 output pin icu6_1 ? input capture ch.6 input pin (1) (mb91f59a/b only) 117 p103 ? c general - purpose i/o port sin5_1 ? lin - uart ch.5 serial data input pin (1) an3 ? adc analog 3 input pin tin3_1 ? reload timer ch.3 event input pin (1) ppg1_1 ? ppg ch.1 output pin (1) icu7_1 ? input capture ch.7 input pin (1) (mb91f59a/b only) 118 p104 ? c general - purpose i/o port sot5_1 ? lin - uart ch.5 serial data output pin (1) an4 ? adc analog 4 input pin tot0_1 ? reload timer ch.0 output pin (1) ppg2_1 ? ppg ch.2 output pin (1) icu8_1 ? input capture ch.8 input pin (1) (mb91f59a/b only) 119 p105 ? c general - purpose i/o port sck5_1 ? lin - uart ch.5 clock i/o pin (1) an5 ? adc analog 5 input pin tot1_1 ? reload timer ch.1 output pin (1) ppg3_1 ? ppg ch.3 output pin (1) icu9_1 ? input capture ch.9 input pin (1) (mb91f59a/b only) 120 p106 ? c general - purpose i/o port sga4_1 ? sound generator ch.4 sga output pin an6 ? adc analog 6 input pin ppg4_1 ? ppg ch.4 output pin (1) tin10_1 ? reload timer ch.10 event input pin (1) (mb91f59a/b only) icu10_1 ? input capture ch.10 input pin (1) (mb91f59a/b only) document number: 002- 04727 rev. *b page 24 of 174 mb91590 series pin no . pin name polarity i/o circuit types *1 function *2 121 p107 ? c general - purpose i/o port sgo4_1 ? sound generator ch.4 sgo output pin an7 ? adc analog 7 input pin ppg5_1 ? ppg ch.5 output pin (1) tot7_1 ? reload timer ch.7 output pin (1) (mb91f59a/b only) icu11_1 ? input capture ch.11 input pin (1) (mb91f59a/b only) 101 p110 ? c general - purpose i/o port tx1 ? can transmission data1 output pin ppg1_2 ? ppg ch.1 output pin (2) frck5 ? free - run timer 5 clock input pin (mb91f59a/b only) tot8_1 ? reload timer ch.8 output pin (1) (mb91f59a/b only) 102 p111 ? c general - purpose i/o port rx1 ? can reception data 1 input pin int10 ? int10 external interrupt input pin ppg2_2 ? ppg ch.2 output pin (2) frck6 ? free - run timer 6 clock input pin (mb91f59a/b only) tot9_1 ? reload timer ch.9 output pin (1) (mb91f59a/b only) 158 p112 ? c general - purpose i/o port tx2 ? can transmission data 2 output pin ppg3_2 ? ppg ch.3 output pin (2) tot10_1 ? reload timer ch.10 output pin (1) (mb91f59a/b only) 159 p113 ? c general - purpose i/o port rx2 ? can reception data 2 input pin int11 ? int11 external interrupt input pin ppg4_2 ? ppg ch.4 output pin (2) tin7 ? reload timer ch.7 event input pin (mb91f59a/b only) 162 p114 ? c general - purpose i/o port sga2 ? sound generator ch.2 sga output pin sck3 ? lin - uart ch.3 clock i/o pin trg3 ? ppg trigger 3 input pin (ch.12 to ch.15) tin1 ? reload timer ch.1 event input pin icu5_1 ? input capture ch.5 input pin (1) frck7 ? free - run timer 7 clock input pin (mb91f59a/b only) 163 p115 ? c general - purpose i/o port sgo2 ? sound generator ch.2 sgo output pin sin4 ? lin - uart ch.4 serial data input pin tin2 ? reload timer ch.2 event input pin frck4 ? free - run timer 4 clock input pin (mb91f59a/b only) 164 p116 ? c general - purpose i/o port sga3 ? sound generator ch.3 sga output pin sot4 ? lin - uart ch.4 serial data output pin tin3 ? reload timer ch.3 event input pin frck3 ? free - run timer 3 clock input pin (mb91f59a/b only) 165 p117 ? c general - purpose i/o port sgo3 ? sound generator ch.3 sgo output pin sck4 ? lin - uart ch.4 clock i/o pin trg4 ? ppg trigger 4 input pin (ch.16 to ch.19) tot0 ? reload timer ch.0 output pin frck2 ? free - run timer 2 clock input pin(mb91f59a/b only) document number: 002- 04727 rev. *b page 25 of 174 mb91590 series pin no . pin name polarity i/o circuit types *1 function *2 166 p120 ? c general - purpose i/o port frck1 ? free - run timer 1 clock input pin sin5 ? lin - uart ch.5 serial data input pin int6 ? int6 external interrupt input pin tot1 ? reload timer ch.1 output pin ppg5_2 ? ppg ch.5 output pin (2) 167 p121 ? c general - purpose i/o port frck0 ? free - run timer 0 clock input pin sot5 ? lin - uart ch.5 serial data output pin int7 ? int7 external interrupt input pin tot2 ? reload timer ch.2 output pin ppg6_2 ? ppg ch.6 output pin (2) 168 p122 ? c general - purpose i/o port ocu0 ? output compare ch.0 output pin sck5 ? lin - uart ch.5 clock i/o pin tot3 ? reload timer ch.3 output pin ppg7_2 ? ppg ch.7 output pin (2) 108 p123 ? a general - purpose i/o port ocu1 ? output compare ch.1 output pin ppg8_2 ? ppg ch.8 output pin (2) tin8 ? reload timer ch.8 event input pin (mb91f59a/b only) sin11 ? multi - function serial ch.11 serial data input pin (mb91f59a/b only) 109 p124 ? a general - purpose i/o port ocu2 ? output compare ch.2 output pin icu5_2 ? input capture ch.5 input pin (2) ppg9_2 ? ppg ch.9 output pin (2) tin9 ? reload timer ch.9 event input pin (mb91f59a/b only) sot11 ? multi - function serial ch.11 serial data output pin (mb91f59a/b only) 110 p125 ? a general - purpose i/o port ocu3 ? output compare ch.3 output pin icu0 ? input capture ch.0 input pin ppg10_2 ? ppg ch.10 output pin (2) tin10 ? reload timer ch.10 event input pin (mb91f59a/b only) sck11 ? multi - function serial ch.11 clock i/o pin (mb91f59a/b only) 90 p126 ? a general - purpose i/o port trg0 ? ppg trigger 0 input pin (ch.0 to ch.3) sin0 ? multi - function serial ch.0 serial data input pin int1 ? int1 external interrupt input pin 91 p127 ? k general - purpose i/o port sot0 ? multi - function serial ch.0 serial data output pin / i 2 c ch.0 serial data i/o pin 92 p130 ? k general - purpose i/o port sck0 ? multi - function serial ch.0 clock i/o pin / i 2 c ch.0 clock i/o pin int0 ? int0 external interrupt input pin icu1 ? input capture ch.1 input pin tioa0 ? base timer tioa0 output pin document number: 002- 04727 rev. *b page 26 of 174 mb91590 series pin no . pin name polarity i/o circuit types *1 function *2 93 p131 ? a general - purpose i/o port trg1 ? ppg trigger 1 input pin (ch.4 to ch.7) sin1 ? multi - function serial ch.1 serial data input pin int4 ? int4 external interrupt input pin icu2 ? input capture ch.2 input pin tioa1 ? base timer tioa1 i/o pin tot7 ? reload timer ch.7 output pin (mb91f59a/b only) 94 p132 ? k general - purpose i/o port sot1 ? multi - function serial ch.1 serial data output pin / i 2 c ch.1 serial data i/o pin int2 ? int2 external interrupt input pin icu3 ? input capture ch.3 input pin tiob0 ? base timer tiob0 input pin tot8 ? reload timer ch.8 output pin (mb91f59a/b only) 95 p133 ? k general - purpose i/o port trg5 ? ppg trigger 5 input pin ( ch.20 to ch.23) ppg11_1 ? ppg ch.11 output pin (1) sck1 ? multi - function serial ch.1 clock i/o pin / i 2 c ch.1 clock i/o pin int3 ? int3 external interrupt input pin icu4 ? input capture ch.4 input pin tiob1 ? base timer tiob1 input pin tot9 ? reload timer ch.9 output pin (mb91f59a/b only) 96 p134 ? a general - purpose i/o port trg2 ? ppg trigger 2 input pin ( ch.8 to ch.11) ppg1_3 ? ppg ch.1 output pin (3) int5 ? int5 external interrupt input pin icu5 ? input capture ch.5 input pin tot10 ? reload timer ch.10 output pin (mb91f59a/b only) 103 debugif ? g debug i/f pin 176 pa2 ? o general - purpose i/o port (3v pin) rin2 ? capture r2 input pin (rgb mode) vin0 ? capture vin0 input pin (656 mode) 177 pa3 ? o general - purpose i/o port (3v pin) rin3 ? capture r3 input pin (rgb mode) vin1 ? capture vin1 input pin (656 mode) 178 pa4 ? o general - purpose i/o port (3v pin) rin4 ? capture r4 input pin (rgb mode) vin2 ? capture vin2 input pin (656 mode) 179 pa5 ? o general - purpose i/o port (3v pin) rin5 ? capture r5 input pin (rgb mode) vin3 ? capture vin3 input pin (656 mode) 180 pa6 ? o general - purpose i/o port (3v pin) rin6 ? capture r6 input pin (rgb mode) vin4 ? capture vin4 input pin (656 mode) 181 pa7 ? o general - purpose i/o port (3v pin) rin7 ? capture r7 input pin (rgb mode) vin5 ? capture vin5 input pin (656 mode) document number: 002- 04727 rev. *b page 27 of 174 mb91590 series pin no . pin name polarity i/o circuit types *1 function *2 182 pb2 ? o general - purpose i/o port (3v pin) gin2 ? capture g2 input pin (rgb mode) vin6 ? capture vin6 input pin (656 mode) 183 pb3 ? o general - purpose i/o port (3v pin) gin3 ? capture g3 input pin (rgb mode) vin7 ? capture vin7 input pin (656 mode) 184 pb4 ? o general - purpose i/o port (3v pin) gin4 ? capture g4 input pin (rgb mode) 185 pb5 ? o general - purpose i/o port (3v pin) gin5 ? capture g5 input pin (rgb mode) 186 pb6 ? o general - purpose i/o port (3v pin) gin6 ? capture g6 input pin (rgb mode) 187 pb7 ? o general - purpose i/o port (3v pin) gin7 ? capture g7 input pin (rgb mode) 190 pc2 ? o general - purpose i/o port (3v pin) bin2 ? capture b2 input pin (rgb mode) 191 pc3 ? o general - purpose i/o port (3v pin) bin3 ? capture b3 input pin (rgb mode) 192 pc4 ? o general - purpose i/o port (3v pin) bin4 ? capture b4 input pin (rgb mode) 193 pc5 ? o general - purpose i/o port (3v pin) bin5 ? capture b5 input pin (rgb mode) 194 pc6 ? o general - purpose i/o port (3v pin) bin6 ? capture b6 input pin (rgb mode) 195 pc7 ? o general - purpose i/o port (3v pin) bin7 ? capture b7 input pin (rgb mode) 2 pd2 ? o general - purpose i/o port (3v pin) rout2 ? display digital r2 output pin 3 pd3 ? o general - purpose i/o port (3v pin) rout3 ? display digital r3 output pin 4 pd4 ? o general - purpose i/o port (3v pin) rout4 ? display digital r4 output pin 5 pd5 ? o general - purpose i/o port (3v pin) rout5 ? display digital r5 output pin 6 pd6 ? o general - purpose i/o port (3v pin) rout6 ? display digital r6 output pin 7 pd7 ? o general - purpose i/o port (3v pin) rout7 ? display digital r7 output pin 8 pe2 ? o general - purpose i/o port (3v pin) gout2 ? display digital g2 output pin 9 pe3 ? o general - purpose i/o port (3v pin) gout3 ? display digital g3 output pin 10 pe4 ? o general - purpose i/o port (3v pin) gout4 ? display digital g4 output pin 11 pe5 ? o general - purpose i/o port (3v pin) gout5 ? display digital g5 output pin 12 pe6 ? o general - purpose i/o port (3v pin) gout6 ? display digital g6 output pin document number: 002- 04727 rev. *b page 28 of 174 mb91590 series pin no . pin name polarity i/o circuit types *1 function *2 13 pe7 ? o general - purpose i/o port (3v pin) gout7 ? display digital g7 output pin 14 pf2 ? o general - purpose i/o port (3v pin) bout2 ? display digital b2 output pin 15 pf3 ? o general - purpose i/o port (3v pin) bout3 ? display digital b3 output pin 16 pf4 ? o general - purpose i/o port (3v pin) bout4 ? display digital b4 output pin 17 pf5 ? o general - purpose i/o port (3v pin) bout5 ? display digital b5 output pin 21 pf6 ? o general - purpose i/o port (3v pin) bout6 ? display digital b6 output pin 22 pf7 ? o general - purpose i/o port(3v pin) bout7 ? display digital b7 output pin 200 pg0 ? o general - purpose i/o port (3v pin) dckin ? display reference clock input pin (for external sync) cmdtrg ? gdc command trigger input pin 197 pg1 ? o general - purpose i/o port (3v pin) vsin p capture vertical sync signal input pin 198 pg2 ? o general - purpose i/o port (3v pin) hsin p capture horizontal sync signal input pin 199 pg3 ? o general - purpose i/o port (3v pin) csout ? display composite sync signal output pin, graphics / video switch (for external sync) output pin 23 pg4 ? o general - purpose i/o port (3v pin) dckout ? display reference clock output pin (for internal sync) 24 pg5 ? o general - purpose i/o port (3v pin) vsync ? display vertical sync signal output pin (for internal sync)/display vertical sync signal input pin (for external sync) 25 pg6 ? o general - purpose i/o port (3v pin) hsync ? display horizontal sync signal output pin (for internal sync)/display horizontal sync signal input pin (for external sync) 26 pg7 ? o general - purpose i/o port (3v pin) deout p display enable display period output pin 196 ph3 ? o general - purpose i/o port (3v pin) cclk ? for capture, capture clock input pin 204 refout ? t clamp level output pin 203 avr3 ? s "l" side reference voltage for ntsc a/d converter pin 205 vin ? s ntsc signal input pin 111 avcc5 ? ? ad convertor analog power supply pin 201, 207 avcc3 ? ? for ntsc, ad convertor analog power supply pin 112 avrh5 ? ? ad convertor upper limit reference voltage pin 113 avss5/ avrl5 ? ? ad convertor gnd/ ad convertor lower limit reference voltage pin 202, 206 avss3 ? ? ntsc ad convertor gnd pin 124 c_1 ? ? built - in regulator capacitor connected pin 1 73 c_2 ? ? built - in regulator capacitor connected pin 2 20 c_3 ? ? built - in regulator capacitor connected pin 3 document number: 002- 04727 rev. *b page 29 of 174 mb91590 series pin no . pin name polarity i/o circuit types *1 function *2 126, 136, 146, 156 dvcc ? ? smc large current port power supply pin 125, 135, 145, 155 dvss ? ? smc large current port gnd pin 89, 105, 122, 173 vcc5 ? ? +5.0v power supply pin 1, 18, 37, 53, 71, 175, 189 vcc3 ? ? +3.3v power supply pin 19, 36, 52, 72, 82, 88, 104, 123, 170, 174, 188, 208 vss ? ? gnd pin *1 : for the i/o circuit types, see " i/o circuit type " . *2 : for switching, see "i/o port" of hardware manual . document number: 002- 04727 rev. *b page 30 of 174 mb91590 series 3.2 mb91f59a/b (bga320) bga pin no. pin name polarity i/o circuit types *1 function *2 1 vss ? ? gnd pin 2 vss ? ? gnd pin 3 avcc3 ? ? for ntsc, ad convertor analog power supply pin 4 vin ? s ntsc signal input pin 5 refout ? t clamp level output pin 6 avcc3 ? ? for ntsc, ad convertor analog power supply pin 7 bin5 ? o capture b5 input pin (rgb mode) pc5 general - purpose i/o port (3v pin) 8 bin2 ? o capture b2 input pin (rgb mode) pc2 general - purpose i/o port (3v pin) 9 gin5 ? o capture g5 input pin (rgb mode) pb5 general - purpose i/o port (3v pin) 10 gin2 ? o capture g2 input pin (rgb mode) vin6 capture vin6 input pin (656 mode) pb2 general - purpose i/o port (3v pin) 11 rin5 ? o capture r5 input pin (rgb mode) vin3 capture vin3 input pin (656 mode) pa5 general - purpose i/o port (3v pin) 12 rin2 ? o capture r2 input pin (rgb mode) vin0 capture vin0 input pin (656 mode) pa2 general - purpose i/o port (3v pin) 13 vss ? ? gnd pin 14 p136 ? a general - purpose i/o port (single clock product) (x1a) n sub clock oscillation output pin (dual clock product) 15 p137 ? a general - purpose i/o port (single clock product) (x0a) ? n sub clock oscillation input pin (dual clock product) 16 vss ? ? gnd pin 17 p094 ? c general - purpose i/o port icu1_1 input capture ch.1 input pin (1) int15 int15 external interrupt input pin sin3 lin - uart ch.3 serial data input pin ppg9_1 ppg ch.9 output pin (1) tin9_1 reload timer ch.9 event input pin (1) sgo1 sound generator ch.1 sgo output pin 18 adtg ? a a/d convertor external trigger input pin p090 general - purpose i/o port ppg0_2 ppg ch.0 output pin (2) tin7_1 reload timer ch.7 event input pin (1) 19 tck ? u test clock (jtag boundary scan test) 20 vss ? ? gnd pin 21 tms ? u test mode state (jtag boundary scan test) 22 tdo ? w test data out (jtag boundary scan test) 23 an31 ? e adc analog 31 input pin p087 general - purpose i/o port icu4_2 input capture ch.4 input pin (2) ppg23 ppg ch.23 output pin 23 pwm2m5 ? e smc ch.5 output pin document number: 002- 04727 rev. *b page 31 of 174 mb91590 series bga pin no. pin name polarity i/o circuit types *1 function *2 24 an28 ? e adc analog 28 input pin p084 general - purpose i/o port icu1_2 input capture ch.1 input pin (2) ppg20 ppg ch.20 output pin pwm1p5 smc ch.5 output pin udcbin2 up/down counter ch.2 bin input pin 25 an25 ? e adc analog 25 input pin p081 general - purpose i/o port sot6 lin - uart ch.6 serial data output pin ppg17 ppg ch.17 output pin pwm1m4 smc ch.4 output pin udcbin0_1 up/down counter ch.0 bin input pin (1) 26 an22 ? e adc analog 22 input pin p076 general - purpose i/o port icu7 input capture ch.7 input pin sot7_1 lin - uart ch.7 serial data output pin ppg14_1 ppg ch.14 output pin (1) pwm2p3 smc ch.3 output pin 27 an19 ? e adc analog 19 input pin p073 general - purpose i/o port icu10 input capture ch.10 input pin sot8 multi - function serial ch.8 serial data output pin pwm2m2 smc ch.2 output pin 28 an16 ? e adc analog 16 input pin p070 general - purpose i/o port sot9 multi - function serial ch.9 serial data output pin pwm1p2 smc ch.2 output pin 29 an13 ? e adc analog 13 input pin p065 general - purpose i/o port pwm1m1 smc ch.1 output pin udczin0 up/down counter ch.0 zin input pin 30 an10 ? e adc analog 10 input pin p062 general - purpose i/o port sck10 multi - function serial ch.10 clock i/o pin pwm2p0 smc ch.0 output pin udczin1 up/down counter ch.1 zin input pin 31 vss ? ? gnd pin 32 c_1 ? ? built - in regulator capacitor connected pin 1 33 an5 ? c adc analog 5 input pin p105 general - purpose i/o port icu9_1 input capture ch.9 input pin (1) sck5_1 lin - uart ch.5 clock i/o pin (1) ppg3_1 ppg ch.3 output pin (1) tot1_1 reload timer ch.1 output pin (1) 34 avss5 ? ? a/d convertor gnd avrl5 a/d convertor lower limit reference voltage pin 35 avrh5 ? ? a/d convertor upper limit reference voltage pin document number: 002- 04727 rev. *b page 32 of 174 mb91590 series bga pin no. pin name polarity i/o circuit types *1 function *2 36 p125 ? a general - purpose i/o port icu0 input capture ch.0 input pin sck11 multi - function serial ch.11 clock i/o pin ocu3 output compare ch.3 output pin ppg10_2 ppg ch.10 output pin (2) tin10 reload timer ch.10 event input pin 37 p123 ? a general - purpose i/o port sin11 multi - function serial ch.11 serial data input pin ocu1 output compare ch.1 output pin ppg8_2 ppg ch.8 output pin (2) tin8 reload timer ch.8 event input pin 38 vss ? ? gnd pin 39 vss ? ? gnd pin 40 md3 ? f3 mode pin 3 41 debugif ? g debug i/f pin 42 tx1 ? c can transmission data1 output pin frck5 free - run timer 5 clock input pin p110 general - purpose i/o port ppg1_2 ppg ch.1 output pin (2) tot8_1 reload timer ch.8 output pin (1) 43 p091 ? c general - purpose i/o port icu2_1 input capture ch.2 input pin (1) int12 int12 external interrupt input pin sin2 lin - uart ch.2 serial data input pin ppg6_1 ppg ch.6 output pin (1) tot2_1 reload timer ch.2 output pin (1) sga0 sound generator ch.0 sga output pin 44 vss ? ? gnd pin 45 x0 ? l main clock oscillation input pin 46 x1 ? l main clock oscillation output pin 47 vss ? ? gnd pin 48 a23 ? o external bus address bit23 output pin p055 general - purpose i/o port (3v pin) spi_sck spi clock output pin 49 a22 ? o external bus address bit22 output pin p054 general - purpose i/o port (3v pin) spi_di spi data input pin 50 c_2 ? ? built - in regulator capacitor connected pin 2 document number: 002- 04727 rev. *b page 33 of 174 mb91590 series bga pin no. pin name polarity i/o circuit types *1 function *2 51 a17 ? o external bus address bit17 output pin p047 general - purpose i/o port (3v pin) qspi_clk hs_spi sclk output pin 52 a15 ? o external bus address bit15 output pin p045 general - purpose i/o port (3v pin) qspi_cs2 hs_spi ssel2 output pin 53 a12 ? o external bus address bit12 output pin p042 general - purpose i/o port (3v pin) 53 qspi_sio3 ? o hs_spi sdata3 i/o pin 54 a09 ? o external bus address bit9 output pin p037 general - purpose i/o port (3v pin) qspi_sio0 hs_spi sdata0 i/o pin 55 a05 ? o external bus address bit5 output pin p033 general - purpose i/o port (3v pin) 56 a02 ? o external bus address bit2 output pin p030 general - purpose i/o port (3v pin) 57 vss ? ? gnd pin 58 vss ? ? gnd pin 59 vss ? ? gnd pin 60 p025 ? o general - purpose i/o port (3v pin) 61 cs1x ? o external bus chip select 1 output pin p022 general - purpose i/o port (3v pin) 62 d15 ? o external bus data bit15 i/o pin p017 general - purpose i/o port (3v pin) 63 gout1 ? o display digital g1 output pin d12 external bus data bit12 i/o pin p014 general - purpose i/o port (3v pin) 64 d8 ? o external bus data bit8 i/o pin p010 general - purpose i/o port (3v pin) 65 d7 ? o external bus data bit7 i/o pin p007 general - purpose i/o port (3v pin) ppg7 ppg ch.7 output pin tot3_2 reload timer ch.3 output pin (2) 66 d4 ? o external bus data bit4 i/o pin p004 general - purpose i/o port (3v pin) sot3_1 lin - uart ch.3 serial data output pin (1) ppg4 ppg ch.4 output pin tot0_2 reload timer ch.0 output pin (2) 67 d1 ? o external bus data bit1 i/o pin p001 general - purpose i/o port (3v pin) sot2_1 lin - uart ch.2 serial data output pin (1) ppg1 ppg ch.1 output pin tin1_2 reload timer ch.1 event input pin (2) 68 dckout ? o display reference clock output pin (for internal sync) pg4 general - purpose i/o port (3v pin) 69 vss ? ? gnd pin 70 c_3 ? ? built - in regulator capacitor connected pin 3 71 bout4 ? o display digital b4 output pin pf4 general - purpose i/o port (3v pin) document number: 002- 04727 rev. *b page 34 of 174 mb91590 series bga pin no. pin name polarity i/o circuit types *1 function *2 72 gout7 ? o display digital g7 output pin pe7 general - purpose i/o port (3v pin) 73 gout4 ? o display digital g4 output pin pe4 general - purpose i/o port (3v pin) 74 rout7 ? o display digital r7 output pin pd7 general - purpose i/o port (3v pin) 75 rout4 ? o display digital r4 output pin pd4 general - purpose i/o port (3v pin) 76 vss ? ? gnd pin 77 vss ? ? gnd pin 78 vss ? ? gnd pin 79 avss3 ? ? ntsc ad convertor gnd pin 80 avr3 ? s "l" side reference voltage for ntsc a/d converter pin 81 avss3 ? ? ntsc ad convertor gnd pin 82 bin6 ? o capture b6 input pin (rgb mode) pc6 general - purpose i/o port (3v pin) 83 bin3 ? o capture b3 input pin (rgb mode) pc3 general - purpose i/o port (3v pin) 84 gin6 ? o capture g6 input pin (rgb mode) pb6 general - purpose i/o port (3v pin) 85 gin3 ? o capture g3 input pin (rgb mode) vin7 capture vin7 input pin (656 mode) pb3 general - purpose i/o port (3v pin) 86 rin6 ? o capture r6 input pin (rgb mode) vin4 capture vin4 input pin (656 mode) pa6 general - purpose i/o port (3v pin) 87 rin3 ? o capture r3 input pin (rgb mode) vin1 capture vin1 input pin (656 mode) pa3 general - purpose i/o port (3v pin) 88 p122 ? c general - purpose i/o port sck5 lin - uart ch.5 clock i/o pin ocu0 output compare ch.0 output pin ppg7_2 ppg ch.7 output pin (2) tot3 reload timer ch.3 output pin 89 vss ? ? gnd pin 90 md2 ? f2 mode pin 2 91 frck7 ? c free - run timer 7 clock input pin p114 general - purpose i/o port icu5_1 input capture ch.5 input pin (1) sck3 lin - uart ch.3 clock i/o pin trg3 ppg trigger 3 input pin (ch.12 to ch.15) tin1 reload timer ch.1 event input pin sga2 sound generator ch.2 sga output pin 92 rx2 ? c can reception data 2 input pin p113 general - purpose i/o port int11 int11 external interrupt input pin ppg4_2 ppg ch.4 output pin (2) tin7 reload timer ch.7 event input pin 93 tdi ? u test data in (jtag boundary scan test) document number: 002- 04727 rev. *b page 35 of 174 mb91590 series bga pin no. pin name polarity i/o circuit types *1 function *2 94 vss ? ? gnd pin 95 trst ? v test reset (jtag boundary scan test) 96 an30 ? e adc analog 30 input pin p086 general - purpose i/o port 96 icu3_2 ? e input capture ch.3 input pin (2) ppg22 ppg ch.22 output pin pwm2p5 smc ch.5 output pin 97 an27 ? e adc analog 27 input pin p083 general - purpose i/o port icu0_2 input capture ch.0 input pin (2) ppg19 ppg ch.19 output pin pwm2m4 smc ch.4 output pin udczin2 up/down counter ch.2 zin input pin 98 an24 ? e adc analog 24 input pin p080 general - purpose i/o port sin6 lin - uart ch.6 serial data input pin ppg16 ppg ch.16 output pin pwm1p4 smc ch.4 output pin udcain0_1 up/down counter ch.0 ain input pin (1) 99 an21 ? e adc analog 21 input pin p075 general - purpose i/o port icu8 input capture ch.8 input pin sin7_1 lin - uart ch.7 serial data input pin ppg13_1 ppg ch.13 output pin (1) pwm1m3 smc ch.3 output pin 100 an18 ? e adc analog 18 input pin p072 general - purpose i/o port icu11 input capture ch.11 input pin sin8 multi - function serial ch.8 serial data input pin pwm2p2 smc ch.2 output pin 101 an15 ? e adc analog 15 input pin p067 general - purpose i/o port sin9 multi - function serial ch.9 serial data input pin pwm2m1 smc ch.1 output pin udcain0 up/down counter ch.0 ain input pin 102 an12 ? e adc analog 12 input pin p064 general - purpose i/o port pwm1p1 smc ch.1 output pin udcain1 up/down counter ch.1 ain input pin 103 an9 ? e adc analog 9 input pin p061 general - purpose i/o port sot10 multi - function serial ch.10 serial data output pin pwm1m0 smc ch.0 output pin 104 vss ? ? gnd pin document number: 002- 04727 rev. *b page 36 of 174 mb91590 series bga pin no. pin name polarity i/o circuit types *1 function *2 105 an7 ? c adc analog 7 input pin p107 general - purpose i/o port icu11_1 input capture ch.11 input pin (1) ppg5_1 ppg ch.5 output pin (1) tot7_1 reload timer ch.7 output pin (1) sgo4_1 sound generator ch.4 sgo output pin 106 an4 ? c adc analog 4 input pin 106 p104 ? c general - purpose i/o port icu8_1 input capture ch.8 input pin (1) sot5_1 lin - uart ch.5 serial data output pin (1) ppg2_1 ppg ch.2 output pin (1) tot0_1 reload timer ch.0 output pin (1) 107 an2 ? c adc analog 2 input pin p102 general - purpose i/o port icu6_1 input capture ch.6 input pin (1) sck4_1 lin - uart ch.4 clock i/o pin (1) ppg10 ppg ch.10 output pin tin2_1 reload timer ch.2 event input pin (1) 108 avcc5 ? ? a/d convertor analog power supply pin 109 p124 ? a general - purpose i/o port icu5_2 input capture ch.5 input pin (2) sot11 multi - function serial ch.11 serial data output pin ocu2 output compare ch.2 output pin ppg9_2 ppg ch.9 output pin (2) tin9 reload timer ch.9 event input pin 110 rx0 ? a can reception data0 input pin p096 general - purpose i/o port int9 int9 external interrupt input pin 111 vss ? ? gnd pin 112 rx1 ? c can reception data 1 input pin frck6 free - run timer 6 clock input pin p111 general - purpose i/o port int10 int10 external interrupt input pin ppg2_2 ppg ch.2 output pin (2) tot9_1 reload timer ch.9 output pin (1) 113 p093 ? c general - purpose i/o port icu3_1 input capture ch.3 input pin (1) int14 int14 external interrupt input pin sot2 lin - uart ch.2 serial data output pin ppg8_1 ppg ch.8 output pin (1) tin8_1 reload timer ch.8 event input pin (1) sga1 sound generator ch.1 sga output pin 114 nmix n f1 non - masking interrupt input pin 115 tioa1 ? a base timer tioa1 i/o pin p131 general - purpose i/o port icu2 input capture ch.2 input pin int4 int4 external interrupt input pin sin1 multi - function serial ch.1 serial data input pin trg1 ppg trigger 1 input pin (ch.4 to ch.7) tot7 reload timer ch.7 output pin document number: 002- 04727 rev. *b page 37 of 174 mb91590 series bga pin no. pin name polarity i/o circuit types *1 function *2 116 md0 ? p mode pin 0 117 md1 ? p mode pin 1 118 p126 ? a general - purpose i/o port int1 int1 external interrupt input pin 118 sin0 ? a multi - function serial ch.0 serial data input pin trg0 ppg trigger 0 input pin (ch.0 to ch.3) 119 a24 ? o external bus address bit24 output pin p056 general - purpose i/o port (3v pin) spi_xcs spi chip select output pin 120 a21 ? o external bus address bit21 output pin p053 general - purpose i/o port(3v pin) spi_do spi data output pin 121 vss ? ? gnd pin 122 a16 ? o external bus address bit16 output pin p046 general - purpose i/o port (3v pin) qspi_cs3 hs_spi ssel3 output pin 123 a14 ? o external bus address bit14 output pin p044 general - purpose i/o port (3v pin) qspi_cs1 hs_spi ssel1 output pin 124 a11 ? o external bus address bit11 output pin p041 general - purpose i/o port (3v pin) qspi_sio2 hs_spi sdata2 i/o pin 125 a08 ? o external bus address bit8 output pin p036 general - purpose i/o port (3v pin) 126 a04 ? o external bus address bit4 output pin p032 general - purpose i/o port (3v pin) 127 a01 ? o external bus address bit1 output pin p027 general - purpose i/o port (3v pin) 128 vss ? ? gnd pin 129 a00 ? o external bus address bit0 output pin p026 general - purpose i/o port (3v pin) 130 rex ? o external bus read enable output pin p023 general - purpose i/o port (3v pin) 131 wex ? o external bus write enable output pin p020 general - purpose i/o port (3v pin) 132 bout0 ? o display digital b0 output pin d13 external bus data bit13 i/o pin p015 general - purpose i/o port (3v pin) 133 rout0 ? o display digital r0 output pin d9 external bus data bit9 i/o pin p011 general - purpose i/o port (3v pin) 134 d6 ? o external bus data bit6 i/o pin p006 general - purpose i/o port (3v pin) ppg6 ppg ch.6 output pin tot2_2 reload timer ch.2 output pin (2) 135 d3 ? o external bus data bit3 i/o pin p003 general - purpose i/o port (3v pin) sin3_1 lin - uart ch.3 serial data input pin (1) ppg3 ppg ch.3 output pin tin3_2 reload timer ch.3 event input pin (2) document number: 002- 04727 rev. *b page 38 of 174 mb91590 series bga pin no. pin name polarity i/o circuit types *1 function *2 136 d0 ? o external bus data bit0 i/o pin 136 p000 ? o general - purpose i/o port (3v pin) sin2_1 lin - uart ch.2 serial data input pin (1) ppg0 ppg ch.0 output pin tin0_2 reload timer ch.0 event input pin (2) 137 vsync ? o display vertical sync signal output pin (for internal sync)/ display vertical sync signal input pin (for external sync) pg5 general - purpose i/o port (3v pin) 138 bout7 ? o display digital b7 output pin pf7 general - purpose i/o port(3v pin) 139 bout5 ? o display digital b5 output pin pf5 general - purpose i/o port (3v pin) 140 bout3 ? o display digital b3 output pin pf3 general - purpose i/o port (3v pin) 141 gout6 ? o display digital g6 output pin pe6 general - purpose i/o port (3v pin) 142 gout3 ? o display digital g3 output pin pe3 general - purpose i/o port (3v pin) 143 rout6 ? o display digital r6 output pin pd6 general - purpose i/o port (3v pin) 144 rout3 ? o display digital r3 output pin pd3 general - purpose i/o port (3v pin) 145 vss ? ? gnd pin 146 dckin ? o display reference clock input pin (for external sync) cmdtrg gdc command trigger input pin pg0 general - purpose i/o port (3v pin) 147 csout ? o display composite sync signal output pin, graphics / video switch (for external sync) output pin pg3 general - purpose i/o port (3v pin) 148 hsin p o capture horizontal sync signal input pin pg2 ? general - purpose i/o port (3v pin) 149 bin7 ? o capture b7 input pin (rgb mode) pc7 general - purpose i/o port (3v pin) 150 bin4 ? o capture b4 input pin (rgb mode) pc4 general - purpose i/o port (3v pin) 151 gin7 ? o capture g7 input pin (rgb mode) pb7 general - purpose i/o port (3v pin) 152 gin4 ? o capture g4 input pin (rgb mode) pb4 general - purpose i/o port (3v pin) 153 rin7 ? o capture r7 input pin (rgb mode) vin5 capture vin5 input pin (656 mode) pa7 general - purpose i/o port (3v pin) 154 rin4 ? o capture r4 input pin (rgb mode) vin2 capture vin2 input pin (656 mode) pa4 general - purpose i/o port (3v pin) 155 frck0 ? c free - run timer 0 clock input pin p121 general - purpose i/o port int7 int7 external interrupt input pin document number: 002- 04727 rev. *b page 39 of 174 mb91590 series bga pin no. pin name polarity i/o circuit types *1 function *2 155 sot5 ? c lin - uart ch.5 serial data output pin ppg6_2 ppg ch.6 output pin (2) tot2 reload timer ch.2 output pin 156 frck1 ? c free - run timer 1 clock input pin p120 general - purpose i/o port int6 int6 external interrupt input pin sin5 lin - uart ch.5 serial data input pin ppg5_2 ppg ch.5 output pin (2) tot1 reload timer ch.1 output pin 157 frck3 ? c free - run timer 3 clock input pin p116 general - purpose i/o port sot4 lin - uart ch.4 serial data output pin tin3 reload timer ch.3 event input pin sga3 sound generator ch.3 sga output pin 158 p097 ? c general - purpose i/o port icu4_1 input capture ch.4 input pin (1) 158 int8 int8 external interrupt input pin sot3 lin - uart ch.3 serial data output pin ppg0_1 ppg ch.0 output pin (1) tin0 reload timer ch.0 event input pin wot rtc overflow output pin 159 tx2 ? c can transmission data 2 output pin p112 general - purpose i/o port ppg3_2 ppg ch.3 output pin (2) tot10_1 reload timer ch.10 output pin (1) 160 vss ? ? gnd pin 161 an29 ? e adc analog 29 input pin p085 general - purpose i/o port icu2_2 input capture ch.2 input pin (2) ppg21 ppg ch.21 output pin pwm1m5 smc ch.5 output pin udcain2 up/down counter ch.2 ain input pin 162 an26 ? e adc analog 26 input pin p082 general - purpose i/o port sck6 lin - uart ch.6 clock i/o pin ppg18 ppg ch.18 output pin pwm2p4 smc ch.4 output pin udczin0_1 up/down counter ch.0 zin input pin (1) 163 an23 ? e adc analog 23 input pin p077 general - purpose i/o port icu6 input capture ch.6 input pin sck7_1 lin - uart ch.7 clock i/o pin ppg15_1 ppg ch.15 output pin (1) pwm2m3 smc ch.3 output pin 164 an20 ? e adc analog 20 input pin p074 general - purpose i/o port icu9 input capture ch.9 input pin 164 sck8 ? e multi - function serial ch.8 clock i/o pin ppg12_1 ppg ch.12 output pin (1) pwm1p3 smc ch.3 output pin document number: 002- 04727 rev. *b page 40 of 174 mb91590 series bga pin no. pin name polarity i/o circuit types *1 function *2 165 an17 ? e adc analog 17 input pin p071 general - purpose i/o port sck9 multi - function serial ch.9 clock i/o pin pwm1m2 smc ch.2 output pin 166 an14 ? e adc analog 14 input pin p066 general - purpose i/o port pwm2p1 smc ch.1 output pin udcbin0 up/down counter ch.0 bin input pin 167 an11 ? e adc analog 11 input pin p063 general - purpose i/o port 167 pwm2m0 smc ch.0 output pin udcbin1 up/down counter ch.1 bin input pin 168 an8 ? e adc analog 8 input pin p060 general - purpose i/o port sin10 multi - function serial ch.10 serial data input pin pwm1p0 smc ch.0 output pin 169 vcc5 ? ? +5.0 v power supply pin 170 an6 ? c adc analog 6 input pin p106 general - purpose i/o port icu10_1 input capture ch.10 input pin (1) ppg4_1 ppg ch.4 output pin (1) tin10_1 reload timer ch.10 event input pin (1) sga4_1 sound generator ch.4 sga output pin 171 an3 ? c adc analog 3 input pin p103 general - purpose i/o port icu7_1 input capture ch.7 input pin (1) sin5_1 lin - uart ch.5 serial data input pin (1) ppg1_1 ppg ch.1 output pin (1) tin3_1 reload timer ch.3 event input pin (1) 172 an1 ? c adc analog 1 input pin p101 general - purpose i/o port sot4_1 lin - uart ch.4 serial data output pin (1) ppg9 ppg ch.9 output pin tin1_1 reload timer ch.1 event input pin (1) 173 an0 ? c adc analog 0 input pin p100 general - purpose i/o port sin4_1 lin - uart ch.4 serial data input pin (1) ppg8 ppg ch.8 output pin tin0_1 reload timer ch.0 event input pin (1) 174 tx0 ? a can transmission data0 output pin p095 general - purpose i/o port ppg10_1 ppg ch.10 output pin (1) 175 vss ? ? gnd pin 176 p092 ? c general - purpose i/o port icu0_1 input capture ch.0 input pin (1) int13 int13 external interrupt input pin sck2 lin - uart ch.2 clock i/o pin ppg7_1 ppg ch.7 output pin (1) tot3_1 reload timer ch.3 output pin (1) sgo0 sound generator ch.0 sgo output pin document number: 002- 04727 rev. *b page 41 of 174 mb91590 series bga pin no. pin name polarity i/o circuit types *1 function *2 177 p134 ? a general - purpose i/o port icu5 input capture ch.5 input pin int5 int5 external interrupt input pin ppg1_3 ppg ch.1 output pin (3) 177 trg2 ppg trigger 2 input pin ( ch.8 to ch.11) tot10 reload timer ch.10 output pin 178 tiob0 ? k base timer tiob0 input pin p132 general - purpose i/o port icu3 input capture ch.3 input pin int2 int2 external interrupt input pin sot1 multi - function serial ch.1 serial data output pin / i 2 c ch.1 serial data i/o pin tot8 reload timer ch.8 output pin 179 tioa0 ? k base timer tioa0 output pin p130 general - purpose i/o port icu1 input capture ch.1 input pin int0 int0 external interrupt input pin sck0 multi - function serial ch.0 clock i/o pin / i 2 c ch.0 clock i/o pin 180 p127 ? k general - purpose i/o port sot0 multi - function serial ch.0 serial data output pin / i 2 c ch.0 serial data i/o pin 181 rstx n f1 external reset input pin 182 rdy ? o external bus wait input pin p057 general - purpose i/o port (3v pin) 183 a20 ? o external bus address bit20 output pin p052 general - purpose i/o port(3v pin) 184 a19 ? o external bus address bit19 output pin p051 general - purpose i/o port(3v pin) 185 a18 ? o external bus address bit18 output pin p050 general - purpose i/o port (3v pin) 186 a13 ? o external bus address bit13 output pin p043 general - purpose i/o port (3v pin) qspi_cs0 hs_spi ssel0 output pin 187 a10 ? o external bus address bit10 output pin p040 general - purpose i/o port (3v pin) qspi_sio1 hs_spi sdata1 i/o pin 188 a07 ? o external bus address bit7 output pin p035 general - purpose i/o port (3v pin) 189 a03 ? o external bus address bit3 output pin 189 p031 ? o general - purpose i/o port (3v pin) 190 vss ? ? gnd pin 191 p024 ? o general - purpose i/o port (3v pin) 192 cs0x ? o external bus chip select 0 output pin p021 general - purpose i/o port (3v pin) 193 bout1 ? o display digital b1 output pin d14 external bus data bit14 i/o pin p016 general - purpose i/o port (3v pin) document number: 002- 04727 rev. *b page 42 of 174 mb91590 series bga pin no. pin name polarity i/o circuit types *1 function *2 194 rout1 ? o display digital r1 output pin d10 external bus data bit10 i/o pin p012 general - purpose i/o port (3v pin) 195 d5 ? o external bus data bit5 i/o pin p005 general - purpose i/o port (3v pin) sck3_1 lin - uart ch.3 clock i/o pin (1) ppg5 ppg ch.5 output pin tot1_2 reload timer ch.1 output pin (2) 196 d2 ? o external bus data bit2 i/o pin p002 general - purpose i/o port (3v pin) sck2_1 lin - uart ch.2 clock i/o pin (1) ppg2 ppg ch.2 output pin tin2_2 reload timer ch.2 event input pin (2) 197 deout p o display enable display period output pin pg7 ? general - purpose i/o port (3v pin) 198 hsync ? o display horizontal sync signal output pin (for internal sync)/ display horizontal sync signal input pin (for external sync) pg6 general - purpose i/o port (3v pin) 199 bout6 ? o display digital b6 output pin pf6 general - purpose i/o port (3v pin) 200 bout2 ? o display digital b2 output pin pf2 general - purpose i/o port (3v pin) 201 gout5 ? o display digital g5 output pin pe5 general - purpose i/o port (3v pin) 202 gout2 ? o display digital g2 output pin pe2 general - purpose i/o port (3v pin) 203 rout5 ? o display digital r5 output pin pd5 general - purpose i/o port (3v pin) 204 rout2 ? o display digital r2 output pin pd2 general - purpose i/o port (3v pin) 205 vss ? ? gnd pin 206 cclk ? o for capture, capture clock input pin ph3 general - purpose i/o port (3v pin) 207 vsin p o capture vertical sync signal input pin pg1 ? general - purpose i/o port (3v pin) 208 vcc3 ? ? +3.3 v power supply pin 209 vss ? ? gnd pin 210 vss ? ? gnd pin 211 vcc3 ? ? +3.3 v power supply pin 212 vcc3 ? ? +3.3 v power supply pin 213 vss ? ? gnd pin 214 vcc5 ? ? +5.0 v power supply pin 215 frck2 ? c free - run timer 2 clock input pin p117 general - purpose i/o port sck4 lin - uart ch.4 clock i/o pin trg4 ppg trigger 4 input pin (ch.16 to ch.19) tot0 reload timer ch.0 output pin sgo3 sound generator ch.3 sgo output pin document number: 002- 04727 rev. *b page 43 of 174 mb91590 series bga pin no. pin name polarity i/o circuit types *1 function *2 216 frck4 ? c free - run timer 4 clock input pin p115 general - purpose i/o port sin4 lin - uart ch.4 serial data input pin tin2 reload timer ch.2 event input pin sgo2 sound generator ch.2 sgo output pin 217 vcc5 ? ? +5.0 v power supply pin 218 vss ? ? gnd pin 219 dvcc ? ? smc large current port power supply pin 220 dvss ? ? smc large current port gnd pin 221 dvcc ? ? smc large current port power supply pin 222 dvss ? ? smc large current port gnd pin 223 dvcc ? ? smc large current port power supply pin 224 dvss ? ? smc large current port gnd pin 225 dvcc ? ? smc large current port power supply pin 226 dvss ? ? smc large current port gnd pin 227 vcc5 ? ? +5.0 v power supply pin 228 vss ? ? gnd pin 229 vcc5 ? ? +5.0 v power supply pin 230 vcc5 ? ? +5.0 v power supply pin 231 vss ? ? gnd pin 232 vss ? ? gnd pin 233 tiob1 ? k base timer tiob1 input pin p133 general - purpose i/o port icu4 input capture ch.4 input pin int3 int3 external interrupt input pin sck1 multi - function serial ch.1 clock i/o pin / i 2 c ch.1 clock i/o pin ppg11_1 ppg ch.11 output pin (1) trg5 ppg trigger 5 input pin ( ch.20 to ch.23) tot9 reload timer ch.9 output pin 234 vcc5 ? ? +5.0 v power supply pin 235 vcc5 ? ? +5.0 v power supply pin 236 vss ? ? gnd pin 237 vss ? ? gnd pin 238 vss ? ? gnd pin 239 vcc3 ? ? +3.3 v power supply pin 240 vcc3 ? ? +3.3 v power supply pin 241 vss ? ? gnd pin 242 vcc3 ? ? +3.3 v power supply pin 243 a06 ? o external bus address bit6 output pin p034 general - purpose i/o port (3v pin) 244 vss ? ? gnd pin 245 vss ? ? gnd pin 246 vcc3 ? ? +3.3 v power supply pin 247 gout0 ? o display digital g0 output pin d11 external bus data bit11 i/o pin p013 general - purpose i/o port (3v pin) 248 vcc3 ? ? +3.3 v power supply pin 249 vss ? ? gnd pin 250 vss ? ? gnd pin document number: 002- 04727 rev. *b page 44 of 174 mb91590 series bga pin no. pin name polarity i/o circuit types *1 function *2 251 vss ? ? gnd pin 252 vcc3 ? ? +3.3 v power supply pin 253 vcc3 ? ? +3.3 v power supply pin 254 vss ? ? gnd pin 255 vcc3 ? ? +3.3 v power supply pin 256 vcc3 ? ? +3.3 v power supply pin 257 gnd ? ? gnd pin : : : : : : : : : : : : : : : 320 gnd ? ? gnd pin * 1 : for the i/o circuit types, see " i/o circuit type ". *2 : for switching, see " i/o port " of hardware manual . document number: 002- 04727 rev. *b page 45 of 174 mb91590 series 4. i/o circuit type type circuit remarks a ? general - purpose i/o port ? output 1ma,2ma ? pull - up resistor control 50k ? pull - down resistor control 50k ? cmos input ? schmitt input ? ttl input ? automotive input c ? analog i/o, general - purpose i/o port ? output 1ma,2ma ? pull - up resistor control 50k ? pull - down resistor control 50k ? cmos input ? schmitt input ? ttl input ? automotive input pull - up control d i gital output d i gital output pull - down control standby control standby control standby control ttl input standby control automotive input cmos input analog input cmos - hys input pull - up control d i gital output d i gital output pull - down control standby control standby control standby control ttl input standby control automotive input cmos input cmos - hys input document number: 002- 04727 rev. *b page 46 of 174 mb91590 series type circuit remarks e ? analog input, general - purpose i/o port ? output 1ma,2ma,30ma (large current for smc) ? pull - up resistor control 50k ? pull - down resistor control 50k ? cmos inpu t ? schmitt input ? ttl input ? automotive input f1 ? schmitt input ? pull - up resistor control 50k (5v cont) f2 ? schmitt input ? pull - down resistor control 50k (5v cont) f3 ? schmitt input ? automotive input ? pull - down resister control 50k (5v cont) cmos-hys input automotive input pull - up control d i gital output d i gital output pull - down control standby control standby control standby control ttl input standby control automotive input cmos input analog input cmos - hys input cmos - hys input cmos - hys input document number: 002- 04727 rev. *b page 47 of 174 mb91590 series type circuit remarks g ? open - drain i/o ? output 25ma (nod) ? ttl input j automotive input k ? analog input, general - purpose i/o port ? output 1ma,2ma,3ma(i 2 c) ? pull - up resistor control 50k ? pull - down resistor control 50k ? cmos input ? schmitt input ? ttl input ? automotive input l main oscillation i/o n sub oscillation i/o standby control input standby control input pull - up control d i gital output d i gital output pull - down control standby control standby control standby control automotive input standby control ttl input cmos input analog input cmos - hys input automotive input ttl input d i gital output document number: 002- 04727 rev. *b page 48 of 174 mb91590 series type circuit remarks o ? output 2ma,5ma,10ma and 20ma ? pull - up resistor control 33k ? pull - down resistor control 33k ? schmitt input ? ttl input p ? mode i/o ? schmitt input s analog input(3v) t analog output(3v) u ? tdi/tms/tck (jtag) ? cmos input ? pull - up resistor control 50k (1.2v cont) cmos input analog output analog input control mode input pull - up control d i gital output d i gital output pull - down control standby control ttl input standby control cmos - hys input document number: 002- 04727 rev. *b page 49 of 174 mb91590 series type circuit remarks v ? trst (jtag) ? cmos input ? pull - up resistor control 50k (1.2v cont) w ? tdo (jtag) in case of boundary scan test mode. ? high impedance state in other case of boundary scan test mode. ? 5ma output cmos input standby control digital output digital output document number: 002- 04727 rev. *b page 50 of 174 mb91590 series 5. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observ ed to minimize the chance of failure a nd to obtain higher reliability from your cypress semiconductor devices. 5.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. ? absolute maximum ratings semiconductor devices can b e permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. ? recommended operating conditions recommended operating conditions ar e normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these range s may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advise d to contact their sales representative beforehand. ? processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/outpu t functions. 1. preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the dev ice, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. 2. protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows . such conditions if present for extended periods of time can dam age the device. therefore, avoid this type of connection. 3. handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be conne cted through an appropriate resistance to a power supply pin or ground pin. ? latch -up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be f ormed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch -up. caution: the occurrence of latch - up not only causes loss of reliability in the semiconductor device, but ca n cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: 1. be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. 2. be sure that abnormal current flows do not occur during the power - on sequence. ? observance of safety regulations and standards most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. ? fail - safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. document number: 002- 04727 rev. *b page 51 of 174 mb91590 series ? precautions related to usage of devices cypress se miconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (s uch as aerospace systems, atomic energy co ntrols, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior approv al. 5.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during solderin g, you should only mount under cypress's recommended conditions. for detailed information abo ut mount conditions, contact your sales representative. ? lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the boar d, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the soldering process usually causes leads to be s ubjected to thermal stres s in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic lead s be verified before mounting. ? surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connec tions caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with cypress ranking of recommended conditions. ? lead - free packaging caution: when ball grid array (bga) packages with sn -ag - cu balls are mounted using sn- pb eutectic soldering, junction strength may be reduced under some conditions of use. ? storage of semiconductor devices because plastic chip packages are fo rmed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reduci ng moisture resistance and causing packages to crack. to prevent, do the following: 1. avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. 2. use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 c and 30 c . when you open dry package that recommends humidity 40% to 70% relative humidity. 3. when necessary, cypress. packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. 4. avoid storing packages where they are exposed to corrosive gases or high levels of dust. ? baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress recommended conditions for baking. condition: 125 c /24 h document number: 002- 04727 rev. *b page 52 of 174 mb91590 series ? static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the fo llowing precautions: 1. maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. 2. electrically ground all conveyors, solder vessels, soldering irons and peripheral eq uipment. 3. eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock lo ads is recommended. 4. ground all fixtures and instruments, or protect with anti - static measures. 5. avoid the use of styrofoam or other highly static - prone materials for storage of completed board assemblies. 5.3 precautions for use environment reliability of semi conductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: 1. humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. 2. discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to pr event discharges. 3. corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or t o protect the devices. 4. radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. 5. smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in other special environmental conditions should c onsult with sales representatives. document number: 002- 04727 rev. *b page 53 of 174 mb91590 series 6. handling devices this section explains the latch - up prevention and treatment of a pin. ? for latch - up prevention if a voltage higher than vcc or a voltage lower than vss is applied to an i/o pin, or if a voltage exceeding the ratings is applied between vcc pin and vss pin, a latch - up may occur in cmos ic. if the latch- up occurs, the power supply current increases excessively and device elements may be damaged by heat. take care to prevent any voltage from exceeding the max imum ratings in device application. also, the analog power supply (avcc5, avrh5), the ntsc power supply (avcc3, avr3), analog input and power supply to high - current output buffer pins must not be exceed the digital power supply (vcc5 or vcc3) when the powe r supply to the analog system and high - current output buffer pins is turned on or off. in the correct power - on sequence of the microcontroller, turn on the digital power supply (vcc5), analog power supplies (avcc5, avrh5), and the power supply of high - curr ent output buffer pins (dvcc) simultaneously. or, turn on the digital power supply (vcc5), and then turn on analog power supplies (avcc5, avrh5) and the power supply of high - current output buffer pins (dvcc). in the correct power - on sequence of gdc, simila rly turn on the digital power supply (vcc3) and the ntsc analog power supply (avcc3) simultaneously. or, turn on the digital power supply (vcc3), and then turn on the ntsc analog power supply (avcc3). ? treatment of unused pins if unused input pins are left open, they may cause a permanent damage to the device due to malfunction or latch - up. connect a 2k resistor to each of unused pins for pull - up or pull - down processing. also, if i/o pins are not used, they must be set to the output state for opening or the y must be set to the input state and treated in the same way as for the input pins. ? power supply pins the device is designed to ensure that if the device contains multiple vcc pin or vss pin, the pins that should be at the same potential are interconnected to prevent latch - up or other malfunctions. further, connect these pins to an external power supply or ground to reduce unwanted radiation, prevent strobe signals from malfunctioning due to a raised ground level, and fulfill the total output current standa rd, etc. as shown in figure 1 , all vss power supply pins must be treated in the similar way. if multiple vcc or vss systems are connected, the device cannot operate correctly even within the guaranteed operating range. figure 1 . power supply input pins the power supply pins should be connected to vcc pin and vss pin of this device at the low impedance from the power supply source. in the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of c pin is recommended to use as a bypass capacitor between the vcc pin and the vss pin. as for bga package product, the solder balls of vss and vcc are placed in the most internal circumference of solder - ball - placement. in order to co nnect bypass capacitor close to these balls, the capacitors had better be implemented on the back side of a system board surface on which bga package is implemented. vss vss vcc vcc vss vcc vcc vss vss vcc document number: 002- 04727 rev. *b page 54 of 174 mb91590 series ? crystal oscillation circuit an external noise to the x0 pin or x1 pin may cause a device m alfunction. the printed circuit board must be designed to lay out the x0 pin and the x1 pin, crystal oscillator (or ceramic resonator), and the bypass capacitor to be grounded to the close positi on to the device. the printed circuit board artwork is recomm ended to surround the x0 pin and x1 pin by ground circuits. ? mode pins (md2, md1, md0) connec t the md2, md1and md0 m ode pin to the vcc pin or vss pin directly. to prevent an erroneous selection of test mode caused by the noise, reduce the pattern length between each mode pin and the vcc pin or vss pin on the printed circuit board. also, use the low - impedance pin connection. ? during power - on to preven t a malfunction of the voltage step - down circuit built in the device, set the voltage rising time to have 50s or longer (between 0.2v and 2.7v) during power - on. ? notes during pll clock operation when the pll clock is selected and if the oscillator is disc onnected or if the input is stopped, this clock may continue to operate at the free running frequency of the self - oscillator circuit built in the pll clock. this operation is not guaranteed. ? treatment of a/d converter power supply pins connect the pins to have avcc5=avrh5=vcc5 and avss5/avrl5=vss even if the a/d converter is not used. also, similarly connect the pins of ntsc a/d converter power supply to have avcc3=vcc3 and avss3=vss. at this time, open vin/refout. ? notes on using external clock an external clock is not supported. none of the external direct clock input can be used for both main clock and sub clock. ? power - on sequence of a/d converter analog inputs be sure to turn on the digital power supply (vcc5) first, and then turn on the a/d converter power supplies (avcc5, avrh5, avrl5) and analog inputs (an0 to an31). also, turn off the a/d converter power supplies and analog inputs first, and then turn off t h e digital power supply (vcc5). when the avrh5 pin voltage is turned on or off, it must not exceed avcc5. even if a common analog input pin is used as an input port, its input voltage must not exceed avcc5. (however, the analog power supply and digital powe r supply can be turned on or off simultaneously.) be sure to similarly turn on the digital power supply (vcc3) first, and then turn on the a/d converter power supply (avcc3) f or ntsc and ntsc inputs (vin, avr). also, turn off the a/d converter power suppli es and analog inputs first, and then turn off the digital power supply (vcc3). ? treatment of power supplies for high current output buffer pins (dvcc, dvss) be sure to turn on the digital power supply (vcc) first, and then turn on the power supplies for hig h current output buffer pins (dvcc, dvss). also, turn off the power supplies for high current output buffer pins first, and then turn off the digital power suppl y (vcc). even if the high current output buffer pins are used as general - purpose ports, the pow er supplies of high current output buffer pins (dvcc, dvss) must be powered. (the power supplies of high current output buffer pins and the digital power supplies can be tu rned on or off simultaneously. ) ? treatment of c pin this device contains a voltage s tep - down circuit. a capacitor must always be connected to the c pin to assure the internal stabilization of the device. for the standard values, see the "recommended operating conditions" of the latest data sheet. ? function switching of a multiplexed port t o switch between the port function and the multiplexed pin function, use the pfr (port function register). ? low - power consumption mode to transit to the sleep mode, watch mode, stop mode, watch mode(power - off) or stop mode(power - off), follow the procedure explained in the "activating the sleep mode, watch mode, or stop mode" or the "activating the watch mode (power - off) or stop mode(power - off)" of " power consumption control". power supply for gdc can be turned off separately from the microcontroller. take the following notes when using a monitor debugger. ? do not set a break point for the low - power consumption transition program. ? do not execute an operation step for the low - power consumption transition program. document number: 002- 04727 rev. *b page 55 of 174 mb91590 series ? precautions when writing to registers includi ng the status flag when writing data in the register that has a status flag (especially, an interrupt request flag) to control function, taking care not to clear its status flag erroneously must be followed. the program must be written not to clear the fla g to the status bit, and then to set the control bits to have the desired value. especially, if multiple control bits are used, the bit instruction cannot be used. (the bit instruction can access to a singl e bit only.) by the byte, half - word, or word acces s, data is written to the control bits and status flag simultaneously. during this time, take care not to clear other bits (in this case, the bits of status flag) erroneously. note : these points can be ignored because the bit instructions to a register which supports rmw are already taken the points into consideration . care must be taken when the bit instruction is used to a register which does not support rmw. document number: 002- 04727 rev. *b page 56 of 174 mb91590 series 7. block diagram ? mb91f591/592/594/596/597/599 f r o m m a s t e r t o s l a ve f r o m m a s t e r t o s l a ve camera pixel f i f o line buffer sprite engine command decoder display controller bus bridge line engine frame buffer video capture n t sc decoder a d c c la mp i/o ( digital rgb) i/o r a m s i g r l d d m a external bus pin (for gdc external memory) rd y , a 00 - 24 , w ex , r ex , c s 0 x , c s 1 x , d 0 - 1 5 i/o (ext. bus) e x t . b u s external l c d f r 81 s c pu core regulator power-on reset cr oscillator i n s t r u c t i o n m p u d a t a d ebug i n t e r f a ce xbs c r o ss ba r s wi t ch xbs on chip bus r a m f l a sh main flash workflash 64kb r a m e c c control ( xbs - r a m ) c a n ( 3 c h ) bus bridge ext.bus i/f r a m e c c control b a ck u p - r a m c a n prescaler r t c / w d t 1 calibration i/o port setting l i n - u a r t ( 6 c h ) free-run timer ( 2 c h ) multi-function serial interface (2ch) input capture ( 6 c h ) output compare(4ch) base-timer ( 2 c h ) pp g ( 24 c h ) a /d converter g d c external control stepping motor controller ( 6 ch ) reload timer ( 4 c h ) watchdog timer (sw and hw) generation and clear of dma transfer request interrupt request batch read interrupt controller delay interrupt r s t x n m i x wo t clock control (clock setting, main timer, sub timer, pll timer) low-voltage detection (ext. power supply low-voltage detection) low-voltage detection (int. power supply low-voltage detection) n m i clock supervisor real time clock external interrupt input ( 16 c h ) bus bridge ( 32 - b i t 16 - b i t ) sound generator ( 5 c h ) cr c 16-bit peripheral bus 16-bit peripheral bus 32-bit peripheral bus peripheral bus bridge operation mode register bus performance counter d m a c b u s m a s t e r regi s t e r on chip bus layer 2 on chip bus layer 1 i/o port r x 0 - 2 , t x 0 - 2 m d0 , m d1 , m d2 , p 12 7 s go 0 - 4 , s g a 0 - 4 i n t 0 - 15 input interception inhibiting signal s o t 2 - 7 , s i n 2 - 7 , s c k 2 - 7 s o t 0 - 1 , s i n 0 - 1 , s c k 0 - 1 i cu 0 - 5 o cu 0 - 3 t io a 0 - 1 , t io b 0 - 1 t r g 0 - 5 , pp g 0 - 2 3 a d t g, a n 0 - 3 1 p w m 1 m 0 - 5 , p w m 1 p 0 - 5 , p w m 2 m 0 - 5 t i n 0 - 3 , t o t 0 - 3 f rc k 0 - 1 wild register 1 6 3 2 i/o port external flash memory (for video) ahb bus bridge asynchro nous type clock control (divide setting), reset control, low-power consumption control asynchronous bus bridge ( p c l k 1 ? p c l k 2 ) asynchronous bus bridge ( p c l k 1 ? p c l k 2 ) document number: 002- 04727 rev. *b page 57 of 174 mb91590 series ? mb91f59a/59b note: i/o of peripheral functions can be confirmed at "pin assignment" and "pin description". f r o m m a s t e r t o s l a ve f r o m m a s t e r t o s l a ve camera pixel f i f o line buffer sprite engine command decoder display controller bus bridge line engine frame buffer video capture n t sc decoder a d c c la mp i/o ( digital rgb) i/o r a m s i g hs-spi r l d d m a external bus pin (for gdc external memory) rd y , a 00 - 24 , w ex , r ex , c s 0 x , c s 1 x , d 0 - 1 5 i/o (ext. bus) e x t . b u s external l c d f r 81 s c pu core regulator power-on reset cr oscillator i n s t r u c t i o n m p u d a t a d ebug i n t e r f a ce xbs c r o ss ba r s wi t ch xbs on chip bus r a m f l a sh main flash workflash 64kb r a m e c c control ( xbs - r a m ) c a n ( 3 c h ) bus bridge ext.bus i/f r a m e c c control b a ck u p - r a m c a n prescaler r t c / w d t 1 calibration i/o port setting l i n - u a r t ( 6 c h ) free-run timer ( 8c h ) multi-function serial interface (6ch) input capture ( 12c h ) output compare(4ch) base-timer ( 2 c h ) pp g ( 24 c h ) a /d converter g d c external control stepping motor controller ( 6 ch ) reload timer (4ch) up/down counter (3ch) reload timer ( 4 c h ) watchdog timer (sw and hw) generation and clear of dma transfer request interrupt request batch read interrupt controller delay interrupt r s t x n m i x wo t clock control (clock setting, main timer, sub timer, pll timer) low-voltage detection (ext. power supply low-voltage detection) low-voltage detection (int. power supply low-voltage detection) n m i clock supervisor real time clock external interrupt input ( 16 c h ) bus bridge ( 32 - b i t 16 - b i t ) sound generator ( 5 c h ) cr c 16-bit peripheral bus 16-bit peripheral bus 32-bit peripheral bus peripheral bus bridge operation mode register bus performance counter d m a c b u s m a s t e r regi s t e r on chip bus layer 2 on chip bus layer 1 i/o port r x 0 - 2 , t x 0 - 2 m d0 , m d1 , m d2 , p 12 7 s go 0 - 4 , s g a 0 - 4 i n t 0 - 15 input interception inhibiting signal s o t 2 - 7 , s i n 2 - 7 , s c k 2 - 7 s o t 0 ,1,8 - 1 1 , s in 0 ,1,8 - 11, s c k 0 ,1,8 - 11 i cu 0 - 5,6-11 o cu 0 - 3 t io a 0 - 1 , t io b 0 - 1 t r g 0 - 5 , pp g 0 - 2 3 a d t g, a n 0 - 3 1 p w m 1 m 0 - 5 , p w m 1 p 0 - 5 , p w m 2 m 0 - 5 t i n 0 - 3 , t o t 0 - 3 f rc k 0 ,1,2 - 7 wild register 1 6 3 2 i/o port external flash memory (for video) ahb bus bridge asynchro nous type clock control (divide setting), reset control, low-power consumption control asynchronous bus bridge ( p c l k 1 ? p c l k 2 ) asynchronous bus bridge ( p c l k 1 ? p c l k 2 ) ramecc control (ahb-ram) ram document number: 002- 04727 rev. *b page 58 of 174 mb91590 series 8. memory map ? memory map mb91f59b 0000 0000 h i/o 0000 4000 h back up ram (8kb) 0000 6000 h i/o 0001 0000 h ram (192kb) 0004 0000 h access inhibit ahb 0007 0000 h flash memory (1024+1024+64) kb 0028 0000 h access inhibit 0033 0000 h workflash (64kb) 0034 0000 h access inhibit 0040 0000 h gdc control + external area (288mb) ahb 1240 0000 h access inhibit 7fff 0000 h ram (64kb) ahb 8000 0000 h access inhibit ffff ffff h document number: 002- 04727 rev. *b page 59 of 174 mb91590 series ? gdc memory map gdc block mb91f59b 0040 0000 h video ram (1792kb) 0000 0000 h i/o 005b 5800 h reserved 0000 4000 h back up ram (8kb) 0000 6000 h i/o 00c0 0000 h command ram (8kb) 00c0 2000 h reserved 0001 0000 h ram (192kb) 00e0 0000 h access prohibit 0230 0000 h reserved (636kb) 0004 0000 h access inhibit ahb 0239 f000 h command (4kb) 023a 0000 h reserved (64kb) 023b 0000 h sig (4kb) 023b 1000 h ntsc (4kb) 023b 2000 h mcnt (4kb) gdc i/o 023b 3000 h memc (4kb) 023b 4000 h hdmac (4kb) 023b 5000 h rld (4kb) 023b 6000 h reserved (64kb) 0007 0000 h flash memory (1024+1024+64) kb 023b 7000 h cmdseq (4kb) 023b 8000 h sprite (32kb) 023c 0000 h gdc_bridge (64kb) 023d 0000 h display (32kb) 023d 8000 h capture (32kb) 023e 0000 h reserved (64kb) 0028 0000 h access inhibit 023f 0000 h draw (32kb) 023f 8000 h reserved (32kb) 0033 0000 h workflash (64kb) 0240 0000 h external flash (64mb) *1) 0034 0000 h access inhibit 063f fffc h 0640 0000 h external flash (192mb) *2) 0040 0000 h gdc control + external area (288mb) ahb 123f fffc h 1240 0000 h access inhibit 7fff 0000 h ram (64kb) ahb 8000 0000 h access inhibit ffff ffff h note: the gdc area is executed mapping with the little endian. *1) parallel interface supports 64mb of memory space from 0240_0000 h to 063f_fffc h for external flash. *2) hs - spi supports additional 192mb of memory space from 0640_0000 h to 123f_ffff h . (hs - spi totally supports 256mb of memory space from 0240_0000h to 123f_ffffh for external flash) document number: 002- 04727 rev. *b page 60 of 174 mb91590 series ? memory map mb91f59a 0000 0000 h i/o 0000 4000 h back up ram (8kb) 0000 6000 h i/o 0001 0000 h ram (192kb) 0004 0000 h access inhibit ahb 0007 0000 h flash memory (1024+512+64) kb 0020 0000 h access inhibit 0033 0000 h workflash (64kb) 0034 0000 h access inhibit 0040 0000 h gdc control + external area (288mb) ahb 1240 0000 h access inhibit 7fff 0000 h ram (64kb) ahb 8000 0000 h access inhibit ffff ffff h document number: 002- 04727 rev. *b page 61 of 174 mb91590 series ? gdc memory map gdc block mb91f59a 0040 0000 h video ram (1792kb) 0000 0000 h i/o 005b 5800 h reserved 0000 4000 h back up ram (8kb) 0000 6000 h i/o 00c0 0000 h command ram (8kb) 00c0 2000 h reserved 0001 0000 h ram (192kb) 00e0 0000 h access prohibit 0230 0000 h reserved (636kb) 0004 0000 h access inhibit ahb 0239 f000 h command (4kb) 023a 0000 h reserved (64kb) 023b 0000 h sig (4kb) 023b 1000 h ntsc (4kb) 023b 2000 h mcnt (4kb) gdc i/o 023b 3000 h memc (4kb) 023b 4000 h hdmac (4kb) 023b 5000 h rld (4kb) 023b 6000 h reserved (64kb) 0007 0000 h flash memory (1024+512+64) kb 023b 7000 h cmdseq (4kb) 023b 8000 h sprite (32kb) 023c 0000 h gdc_bridge (64kb) 023d 0000 h display (32kb) 023d 8000 h capture (32kb) 023e 0000 h reserved (64kb) 0020 0000 h access inhibit 023f 0000 h draw (32kb) 023f 8000 h reserved (32kb) 0033 0000 h workflash (64kb) 0240 0000 h external flash (64mb) *1) 0034 0000 h access inhibit 063f fffc h 0640 0000 h external flash (192mb) *2) 0040 0000 h gdc control + external area (288mb) ahb 123f fffc h 1240 0000 h access inhibit 7fff 0000 h ram (64kb) ahb 8000 0000 h access inhibit ffff ffff h note: the gdc area is executed mapping with the little endian. *1) parallel interface supports 64mb of memory space from 0240_0000 h to 063f_fffc h for external flash. *2) hs - spi supports additional 192mb of memory space from 0640_0000 h to 123f_fffc h . (hs - spi totally supports 256mb of memory space from 0240_0000 h to 123f_fffc h for external flash) document number: 002- 04727 rev. *b page 62 of 174 mb91590 series ? memory map mb91f594, mb91f599 0000 0000 h i/o 0000 4000 h back up ram (8kb) 0000 6000 h i/o 0001 0000 h ram (64kb) 0002 0000 h reserved 0003 0000 h access inhibit ahb 0007 0000 h flash memory (1024+64) kb 0018 0000 h access inhibit 0023 0000 h workflash (64kb) 0024 0000 h access inhibit 0040 0000 h gdc control + external area (96mb) ahb 0640 0000 h access inhibit 8000 0000 h ffff ffff h document number: 002- 04727 rev. *b page 63 of 174 mb91590 series ? gdc memory map gdc block mb91f594, mb91f599 0040 0000 h video ram (800kb) 0000 0000 h i/o 004c 8000 h reserved 0000 4000 h back up ram (8kb) 0000 6000 h i/o 00c0 0000 h command ram (8kb) 00c0 2000 h reserved 0001 0000 h ram (64kb) 00e0 0000 h access prohibit 0230 0000 h reserved (636kb) 0002 0000 h reserved 0239 f000 h command (4kb) 023a 0000 h reserved (64kb) 023b 0000 h sig (4kb) 0003 0000 h access inhibit ahb 023b 1000 h ntsc (4kb) 023b 2000 h mcnt (4kb) gdc i/o 023b 3000 h memc (4kb) 023b 4000 h hdmac (4kb) 023b 5000 h rld (4kb) 023b 6000 h reserved (64kb) 0007 0000 h flash memory (1024+64) kb 023b 7000 h cmdseq (4kb) 023b 8000 h sprite (32kb) 023c 0000 h gdc_bridge (64kb) 023d 0000 h display (32kb) 023d 8000 h capture (32kb) 023e 0000 h reserved (64kb) 0018 0000 h access inhibit 023f 0000 h draw (32kb) 023f 8000 h reserved (32kb) 0023 0000 h workflash (64kb) 0240 0000 h external flash (64mb) 0024 0000 h access inhibit 063f fffc h 0040 0000 h gdc control + external area (96mb) ahb 0640 0000 h access inhibit 8000 0000 h ffff ffff h note: the gdc area is executed mapping with the little endian. document number: 002- 04727 rev. *b page 64 of 174 mb91590 series ? memory map mb91f592, mb91f597 0000 0000 h i/o 0000 4000 h back up ram (8kb) 0000 6000 h i/o 0001 0000 h ram (40kb) 0001 a000 h reserved 0003 0000 h access inhibit ahb 0007 0000 h flash memory (512+64) kb 0010 0000 h access inhibit 0023 0000 h workflash (64kb) 0024 0000 h access inhibit 0040 0000 h gdc control + external area (96mb) ahb 0640 0000 h access inhibit 8000 0000 h ffff ffff h document number: 002- 04727 rev. *b page 65 of 174 mb91590 series ? gdc memory map gdc block mb91f592, mb91f597 0040 0000 h video ram (800kb) 0000 0000 h i/o 004c 8000 h reserved 0000 4000 h back up ram (8kb) 0000 6000 h i/o 00c0 0000 h command ram (8kb) 00c0 2000 h reserved 0001 0000 h ram (40kb) 00e0 0000 h access inhibit 0230 0000 h reserved (636kb) 0001 a000 h reserved 0239 f000 h command( 4kb) 023a 0000 h reserved (64kb) 023b 0000 h sig (4kb) 0003 0000 h access inhibit ahb 023b 1000 h ntsc (4kb) 023b 2000 h mcnt (4kb) gdc i/o 023b 3000 h memc (4kb) 023b 4000 h hdmac (4kb) 023b 5000 h rld (4kb) 023b 6000 h reserved (64kb) 0007 0000 h flash memory (512+64) kb 023b 7000 h cmdseq (4kb) 023b 8000 h sprite (32kb) 023c 0000 h gdc_bridge (64kb) 023d 0000 h display (32kb) 023d 8000 h capture (32kb) 023e 0000 h reserved (64kb) 0010 0000 h access inhibit 023f 0000 h draw (32kb) 023f 8000 h reserved (32kb) 0023 0000 h workflash (64kb) 0240 0000 h external flash (64mb) 0024 0000 h access inhibit 063f fffc h 0040 0000 h gdc control + external area (96mb) ahb 0640 0000 h access inhibit 8000 0000 h ffff ffff h note: the gdc area is executed mapping with the little endian. document number: 002- 04727 rev. *b page 66 of 174 mb91590 series ? memory map mb91f591, mb91f596 0000 0000 h i/o 0000 4000 h back up ram (8kb) 0000 6000 h i/o 0001 0000 h ram (40kb) 0001 a000 h reserved 0003 0000 h access inhibit ahb 0007 0000 h flash memory (512+64) kb 0010 0000 h access inhibit 0023 0000 h workflash (64kb) 0024 0000 h access inhibit 0040 0000 h gdc control + external area (96mb) ahb 0640 0000 h access inhibit 8000 0000 h ffff ffff h document number: 002- 04727 rev. *b page 67 of 174 mb91590 series ? gdc memory map gdc block mb91f591, mb91f596 0040 0000 h video ram (260kb) 0000 0000 h i/o 0044 1000 h reserved 0000 4000 h back up ram (8kb) 0000 6000 h i/o 00c0 0000 h command ram (8kb) 00c0 2000 h reserved 0001 0000 h ram (40kb) 00e0 0000 h access prohibit 0230 0000 h reserved (636kb) 0001 a000 h reserved 0239 f000 h command (4kb) 023a 0000 h reserved (64kb) 023b 0000 h sig (4kb) 0003 0000 h access inhibit ahb 023b 1000 h ntsc (4kb) 023b 2000 h mcnt (4kb) gdc i/o 023b 3000 h memc (4kb) 023b 4000 h hdmac (4kb) 023b 5000 h rld (4kb) 023b 6000 h reserved (64kb) 0007 0000 h flash memory (512+64) kb 023b 7000 h cmdseq (4kb) 023b 8000 h sprite (32kb) 023c 0000 h gdc_bridge (64kb) 023d 0000 h display (32kb) 023d 8000 h capture (32kb) 023e 0000 h reserved (64kb) 0010 0000 h access inhibit 023f 0000 h draw (32kb) 023f 8000 h reserved (32kb) 0023 0000 h workflash (64kb) 0240 0000 h external flash (64mb) 0024 0000 h access inhibit 063f fffc h 0040 0000 h gdc control + external area (96mb) ahb 0640 0000 h access inhibit 8000 0000 h ffff ffff h note: the gdc area is executed mapping with the little endian. document number: 002- 04727 rev. *b page 68 of 174 mb91590 series 9. i/o map the following i/o map shows the relationship between memory space and registers for peripheral resources. ? legend of i/o map read/write attribute (r: read w: write) address address offset value / register name block +0 +1 +2 +3 000090 h bt1tmr[r] h 00000000 00000000 bt1tmcr[r/w]b,h,w 00000000 00000000 base timer 1 000094 h - bt1stc[r/w] b 00000000 - - 000098 h bt1pcsr/bt1prll[r /w] h 00000000 00000000 bt1pdut/bt1prlh/bt1dtbf[r/w] h 00000000 00000000 00009c h btsel[r/w] b ---- 000 0 - btsssr[w] b,h -------- ------ 11 0000a0 h aderh [r/w]b, h, w 00000000 00000000 aderl [r/w]b, h, w 00000000 00000000 a/d converter 0000a4 h adcs1 [r/w] b, h,w 00000000 adcs0 [r/w] b, h,w 00000000 adcr1 [r] b, h,w ------ xx adcr0 [r] b, h,w xxxxx xxx 0000a8 h adct1 [r/w] b, h,w 00010000 adct0 [r/w] b, h,w 00101100 adsch [r/w] b, h,w --- 00000 adech [r/w] b, h,w --- 00000 data access attribute b: byte h: half - word w: word (note) the access by the data access attribute not described is disabled. initial register value after reset the initial register value after reset indicates as follows: ? "1": initial value "1" ? "0": initial value "0" ? "x": initial value undefined ? " - ": reserved bit/undefined bit ? "*": initial value "0" or "1" according to the setting note: the access by the data access attribute not described is disabled. document number: 002- 04727 rev. *b page 69 of 174 mb91590 series ? i/o map address address offset value / register name block +0 +1 +2 +3 000000 h pdr00[r/w] b,h,w xxxxxxxx pdr01[r/w] b,h,w xxxxxxxx pdr02[r/w] b,h,w xxxxxxxx pdr03[r/w] b,h,w xxxxxxxx port data register 000004 h pdr04[r/w] b,h,w xxxxxxxx pdr05[r/w] b,h,w xxxxxxxx pdr06[r/w] b,h,w xxxxxxxx pdr07[r/w] b,h,w xxxxxxxx 000008 h pdr08[r/w] b,h,w xxxxxxxx pdr09[r/w] b,h,w xxxxxxxx pdr10[r/w] b,h,w xxxxxxxx pdr11[r/w] b,h,w xxxxxxxx 00000c h pdr12[r/w] b,h,w xxxxxxxx pdr13[r/w] b,h,w xx - xxxxx D D 000010 h pdra[r/w] b,h,w xxxxxx -- pdrb[r/w] b,h,w xxxxxx -- pdrc[r/w] b,h,w xxxxxx -- pdrd[r/w] b,h,w xxxxxx -- 000014 h pdre[r/w] b,h,w xxxxxx -- pdrf[r/w] b,h,w xxxxxx -- pdrg[r/w] b,h,w xxxxxxxx pdrh[r/w] b,h,w ---- x --- 000018 h to 000028 h D D D D reserved 00002c h to 000030 h D D D D reserved 000034 h to 000038 h D D D D reserved 00003c h wdtcr0[r/w] b,h,w - 0 -- 0000 wdtcpr0[w] b,h,w 00000000 wdtcr1[r] b,h,w ---- 0110 wdtcpr1[w] b,h,w 00000000 watchdog timer [s] 000040 h D D D D D D D delay interrupt 000048 h to 00005c h D D D D reserved 000060 h tmrlra0 [r/w] h xxxxxxxx xxxxxxxx tmr0 [r] h xxxxxxxx xxxxxxxx reload timer 0 000064 h tmrlrb0 [r/w] h xxxxxxxx xxxxxxxx tmcsr0 [r/w] b, h,w 00000000 0 - 000000 000068 h to 00007c h D D D D reserved 000080 h bt0tmr [r] h 00000000 00000000 bt0tmcr [r/w] h - 0000000 00000000 base timer 0 000084 h D bt0stc [r/w] b 0000 - 000 D D 000088 h bt0pcsr/bt0prll [r/w] h xxxxxxxx xxxxxxxx bt0pdut/bt0prlh/bt0dtbf [r/w] h xxxxxxxx xxxxxxxx 00008c h D D D D document number: 002- 04727 rev. *b page 70 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000090 h bt1tmr [r] h 00000000 00000000 bt1tmcr [r/w] h - 0000000 00000000 base timer 1 000094 h D bt1stc [r/w] b 0000 - 000 D D 000098 h bt1pcsr/bt1prll [r/w] h 00000000 00000000 bt1pdut/bt1prlh/bt1dtbf [r/w] h 00000000 00000000 00009c h btsel01 [r/w] b ---- 0000 D btsssr [w] b,h -------- ------ 11 base timer 0,1 0000a0 h aderh [r/w] b, h, w 00000000 00000000 aderl [r/w] b, h, w 00000000 00000000 a/d converter 0000a4 h adcs1 [r/w] b, h,w 0000000 - adcs0 [r/w] b, h,w 00000000 adcr1 [r] b, h,w ------ xx adcr0 [r] b, h,w xxxxxxxx 0000a8 h adct1 [r/w] b, h,w 00010000 adct0 [r/w] b, h,w 00101100 adsch [r/w] b, h,w --- 00000 adech [r/w] b, h,w --- 00000 0000ac h D D D D D / (ismk0) [r/w] D / (isba0) [r/w] D D 0000bc h fcr10 [r/w] b,h,w --- 00100 fcr00 [r/w] b,h,w - 0000000 fbyte20 [r/w] b,h,w 00000000 fbyte10 [r/w] b,h,w 00000000 0000c0 h scr1/(ibcr1) [r/w] b,h,w 0 -- 00000 smr1 [r/w] b,h,w 000 - 0000 ssr1 [r/w] b,h,w 0 - 000011 escr1/(ibsr1) [r/w] b,h,w - 0000000 multi - function serial 1 *1: byte access is possible only for access to lower 8 bits *2: reserved because i 2 c mode is not set immediately after reset. 0000c4 h rdr1/(tdr1)[r/w] b,h,w *1 ------- 0 00000000 bgr1 [r/w] h,w 00000000 00000000 0000c8 h D / (ismk1) [r/w] D /( isba1) [r/w] D D 0000cc h fcr11 [r/w] b, h, w --- 00100 fcr01[r/w] b, h, w - 0000000 fbyte21 [r/w] b,h,w 00000000 fbyte11[r/w] b,h,w 00000000 0000d0 h scr2 [r/w] b, h, w 00000000 smr2 [r/w] b, h, w 00000000 ssr2 [r/w] b, h, w 00001000 rdr2 /tdr2 [r/w] b, h, w 00000000 lin - uart2 0000d4 h escr2 [r/w] b, h, w 00000x00 eccr2 [r/w] b, h, w - 0000 - xx bgr2 [r/w] b, h, w - 0000000 00000000 0000d8 h scr3 [r/w] b, h, w 00000000 smr3 [r/w] b, h, w 00000000 ssr3 [r/w] b, h, w 00001000 rdr3 /tdr3 [r/w] b, h, w 00000000 lin - uart3 0000dc h escr3 [r/w] b, h, w 00000x00 eccr3 [r/w] b, h, w - 0000 - xx bgr3 [r/w] b, h, w - 0000000 00000000 document number: 002- 04727 rev. *b page 71 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 0000e0 h scr4 [r/w] b, h, w 00000000 smr4 [r/w] b, h, w 00000000 ssr4 [r/w] b, h, w 00001000 rdr4 /tdr4 [r/w] b, h, w 00000000 lin - uart4 0000e4 h escr4 [r/w] b, h, w 00000x00 eccr4 [r/w] b, h, w - 0000 - xx bgr4 [r/w] b, h, w - 0000000 00000000 0000e8 h scr5 [r/w] b, h, w 00000000 smr5 [r/w] b, h, w 00000000 ssr5 [r/w] b, h, w 00001000 rdr5 /tdr5 [r/w] b, h, w 00000000 lin - uart5 0000ec h escr5 [r/w] b, h, w 00000x00 eccr5 [r/w] b, h, w - 0000 - xx bgr5 [r/w] b, h, w - 0000000 00000000 0000f0 h scr6 [r/w] b, h, w 00000000 smr6 [r/w] b, h, w 00000000 ssr6 [r/w] b, h, w 00001000 rdr6 /tdr6 [r/w] b, h, w 00000000 lin - uart6 0000f4 h escr6 [r/w] b, h, w 00000x00 eccr6 [r/w] b, h, w - 0000 - xx bgr6 [r/w] b, h, w - 0000000 00000000 0000f8 h scr7 [r/w] b, h, w 00000000 smr7 [r/w] b, h, w 00000000 ssr7 [r/w] b, h, w 00001000 rdr7 /tdr7 [r/w] b, h, w 00000000 lin - uart7 0000fc h escr7 [r/w] b, h, w 00000x00 eccr7 [r/w] b, h, w - 0000 - xx bgr7 [r/w] b, h, w - 0000000 00000000 000100 h tmrlra1 [r/w] h xxxxxxxx xxxxxxxx tmr1 [r] h xxxxxxxx xxxxxxxx reload timer 1 000104 h tmrlrb1 [r/w] h xxxxxxxx xxxxxxxx tmcsr1 [r/w] b, h,w 00000000 0 - 000000 000108 h tmrlra2 [r/w] h xxxxxxxx xxxxxxxx tmr2 [r] h xxxxxxxx xxxxxxxx reload timer 2 00010c h tmrlrb2 [r/w] h xxxxxxxx xxxxxxxx tmcsr2 [r/w] b, h,w 00000000 0 - 000000 000110 h tmrlra3 [r/w] h xxxxxxxx xxxxxxxx tmr3 [r] h xxxxxxxx xxxxxxxx reload timer 3 000114 h tmrlrb3 [r/w] h xxxxxxxx xxxxxxxx tmcsr3 [r/w] b, h,w 00000000 0 - 000000 000118 h to 000140 h D D D D reserved 000144 h gcn13 [r/w] h 00110010 00010000 D gcn23 [r/w] b ---- 0000 ppg12,13,14,15 control 000148 h gcn14 [r/w] h 00110010 00010000 D gcn24 [r/w] b ---- 0000 ppg16,17,18,19 control 00014c h gcn15 [r/w] h 00110010 00010000 D gcn25 [r/w] b ---- 0000 ppg20,21,22,23 control 000150 h ptmr11 [r] h,w 11111111 11111111 pcsr11 [w] h, w xxxxxxxx xxxxxxxx ppg11 000154 h pdut11 [w] h,w xxxxxxxx xxxxxxxx pcn11 [r/w] b, h,w 0000000 - 000000 - 0 document number: 002- 04727 rev. *b page 72 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000158 h ptmr12 [r] h,w 11111111 11111111 pcsr12 [w] h,w xxxxxxxx xxxxxxxx ppg12 00015c h pdut12 [w] h,w xxxxxxxx xxxxxxxx pcn12 [r/w] b, h,w 0000000 - 000000 - 0 000160 h ptmr13 [r] h,w 11111111 11111111 pcsr13 [w] h,w xxxxxxxx xxxxxxxx ppg13 000164 h pdut13 [w] h,w xxxxxxxx xxxxxxxx pcn13 [r/w] b, h,w 0000000 - 000000 - 0 000168 h ptmr14 [r] h,w 11111111 11111111 pcsr14 [w] h,w xxxxxxxx xxxxxxxx ppg14 00016c h pdut14 [w] h,w xxxxxxxx xxxxxxxx pcn14 [r/w] b, h,w 0000000 - 000000 - 0 000170 h ptmr15 [r] h,w 11111111 11111111 pcsr15 [w] h,w xxxxxxxx xxxxxxxx ppg15 000174 h pdut15 [w] h,w xxxxxxxx xxxxxxxx pcn15 [r/w] b, h,w 0000000 - 000000 - 0 000178 h ptmr16 [r] h,w 11111111 11111111 pcsr16 [w] h, w xxxxxxxx xxxxxxxx ppg16 00017c h pdut16 [w] h,w xxxxxxxx xxxxxxxx pcn16 [r/w] b, h,w 0000000 - 000000 - 0 000180 h ptmr17 [r] h,w 11111111 11111111 pcsr17 [w] h,w xxxxxxxx xxxxxxxx ppg17 000184 h pdut17 [w] h,w xxxxxxxx xxxxxxxx pcn17 [r/w] b, h,w 0000000 - 000000 - 0 000188 h ptmr18 [r] h,w 11111111 11111111 pcsr18 [w] h,w xxxxxxxx xxxxxxxx ppg18 00018c h pdut18 [w] h,w xxxxxxxx xxxxxxxx pcn18 [r/w] b, h,w 0000000 - 000000 - 0 000190 h ptmr19 [r] h,w 11111111 11111111 pcsr19 [w] h,w xxxxxxxx xxxxxxxx ppg19 000194 h pdut19 [w] h,w xxxxxxxx xxxxxxxx pcn19 [r/w] b, h,w 0000000 - 000000 - 0 000198 h ptmr20 [r] h,w 11111111 11111111 pcsr20 [w] h,w xxxxxxxx xxxxxxxx ppg20 00019c h pdut20 [w] h,w xxxxxxxx xxxxxxxx pcn20 [r/w] b, h,w 0000000 - 000000 - 0 0001a0 h ptmr21 [r] h,w 11111111 11111111 pcsr21 [w] h, w xxxxxxxx xxxxxxxx ppg21 0001a4 h pdut21 [w] h,w xxxxxxxx xxxxxxxx pcn21 [r/w] b, h,w 0000000 - 000000 - 0 0001a8 h ptmr22 [r] h,w 11111111 11111111 pcsr22 [w] h,w xxxxxxxx xxxxxxxx ppg22 0001ac h pdut22 [w] h,w xxxxxxxx xxxxxxxx pcn22 [r/w] b, h,w 0000000 - 000000 - 0 0001b0 h ptmr23 [r] h,w 11111111 11111111 pcsr23 [w] h,w xxxxxxxx xxxxxxxx ppg23 0001b4 h pdut23 [w] h,w xxxxxxxx xxxxxxxx pcn23 [r/w] b, h,w 0000000 - 000000 - 0 0001b8 h tmrlra7 [r/w] h xxxxxxxx xxxxxxxx tmr7 [r] h xxxxxxxx xxxxxxxx reload timer 7 mb91f59a/b only 0001bc h tmrlrb7 [r/w] h xxxxxxxx xxxxxxxx tmcsr7 [r/w] b, h,w 00000000 0 - 000000 document number: 002- 04727 rev. *b page 73 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 0001c0 h tmrlra8 [r/w] h xxxxxxxx xxxxxxxx tmr8 [r] h xxxxxxxx xxxxxxxx reload timer 8 mb91f59a/b only 0001c4 h tmrlrb8 [r/w] h xxxxxxxx xxxxxxxx tmcsr8 [r/w] b, h,w 00000000 0 - 000000 0001c8 h tmrlra9 [r/w] h xxxxxxxx xxxxxxxx tmr9 [r] h xxxxxxxx xxxxxxxx reload timer 9 mb91f59a/b only 0001cc h tmrlrb9 [r/w] h xxxxxxxx xxxxxxxx tmcsr9 [r/w] b, h,w 00000000 0 - 000000 0001d0 h tmrlra10 [r/w] h xxxxxxxx xxxxxxxx tmr10 [r] h xxxxxxxx xxxxxxxx reload timer 10 mb91f59a/b only 0001d4 h tmrlrb10 [r/w] h xxxxxxxx xxxxxxxx tmcsr10 [r/w] b, h,w 00000000 0 - 000000 0001d8 h to 0001dc h D D D D reserved 0001e0 h scr10 [r/w] b,h,w 0 -- 00000 smr10 [r/w] b,h,w 000 - 0000 ssr10 [r/w] b,h,w 0 - 000011 escr10 [r/w] b,h,w - 0000000 multi - function serial 10 *1: byte access is possible only for access to lower 8 bits. mb91f59a/b only 0001e4 h rdr10/(tdr10)[r/w] b,h,w *1 ------- 0 00000000 bgr10 [r/w] h,w 00000000 00000000 0001e8 h D D D D D D D D document number: 002- 04727 rev. *b page 74 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000200 h pwc20 [r/w] h,w ------ xx xxxxxxxx pwc10 [r/w] h,w ------ xx xxxxxxxx stepping motor controller 000204 h D pwc0 [r/w] b - 00000-- pws20 [r/w] b,h,w - 0000000 pws10 [r/w] b,h,w -- 000000 000208 h pwc21 [r/w] h,w ------ xx xxxxxxxx pwc11 [r/w] h,w ------ xx xxxxxxxx 00020c h D pwc1 [r/w] b - 00000-- pws21 [r/w] b,h,w - 0000000 pws11 [r/w] b,h,w -- 000000 000210 h pwc22 [r/w] h,w ------ xx xxxxxxxx pwc12 [r/w] h,w ------ xx xxxxxxxx 000214 h D pwc2 [r/w] b - 00000-- pws22 [r/w] b,h,w - 0000000 pws12 [r/w] b,h,w -- 000000 000218 h pwc23 [r/w] h,w ------ xx xxxxxxxx pwc13 [r/w] h,w ------ xx xxxxxxxx 00021c h D pwc3 [r/w] b - 00000-- pws23 [r/w] b,h,w - 0000000 pws13 [r/w] b,h,w -- 000000 000220 h pwc24 [r/w] h,w ------ xx xxxxxxxx pwc14 [r/w] h,w ------ xx xxxxxxxx 000224 h D pwc4 [r/w] b - 00000-- pws24 [r/w] b,h,w - 0000000 pws14 [r/w] b,h,w -- 000000 000228 h pwc25 [r/w] h,w ------ xx xxxxxxxx pwc15 [r/w] h,w ------ xx xxxxxxxx 00022c h D pwc5 [r/w] b - 00000-- pws25 [r/w] b,h,w - 0000000 pws15 [r/w] b,h,w -- 000000 000230 h to 00023c h D D D D reserved 000240 h cpclr0 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 0 000244 h tcdt0 [r/w] w 00000000 00000000 00000000 00000000 000248 h tccsh0 [r/w]b, h, w 0 ----- 00 tccsl0 [r/w]b, h, w - 1 - 00000 D 00024c h cpclr1 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 1 000250 h tcdt1 [r/w] w 00000000 00000000 00000000 00000000 000254 h tccsh1 [r/w]b, h, w 0 ----- 00 tccsl1 [r/w]b, h, w - 1 - 00000 D 000258 h D D D D D gcn20 [r/w] b ---- 0000 ppg0,1,2,3 control 000260 h gcn11 [r/w] h 00110010 00010000 D gcn21 [r/w] b ---- 0000 ppg4,5,6,7 control 000264 h gcn12 [r/w] h 00110010 00010000 D gcn22 [r/w] b ---- 0000 ppg8,9,10,11 control document number: 002- 04727 rev. *b page 75 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000268 h D D D ppgdiv [r/w] b ------ 00 ppg0 00026c h ptmr0 [r] h,w 11111111 11111111 pcsr0 [w] h,w xxxxxxxx xxxxxxxx 000270 h pdut0 [w] h,w xxxxxxxx xxxxxxxx pcn0 [r/w] b, h,w 0000000 - 000000 - 0 000274 h ptmr1 [r] h,w 11111111 11111111 pcsr1 [w] h, w xxxxxxxx xxxxxxxx ppg1 000278 h pdut1 [w] h,w xxxxxxxx xxxxxxxx pcn1 [r/w] b, h,w 0000000 - 000000 - 0 00027c h ptmr2 [r] h,w 11111111 11111111 pcsr2 [w] h,w xxxxxxxx xxxxxxxx ppg2 000280 h pdut2 [w] h,w xxxxxxxx xxxxxxxx pcn2 [r/w] b, h,w 0000000 - 000000 - 0 000284 h ptmr3 [r] h,w 11111111 11111111 pcsr3 [w] h,w xxxxxxxx xxxxxxxx ppg3 000288 h pdut3 [w] h,w xxxxxxxx xxxxxxxx pcn3 [r/w] b, h,w 0000000 - 000000 - 0 00028c h ptmr4 [r] h,w 11111111 11111111 pcsr4 [w] h,w xxxxxxxx xxxxxxxx ppg4 000290 h pdut4 [w] h,w xxxxxxxx xxxxxxxx pcn4 [r/w] b, h,w 0000000 - 000000 - 0 000294 h ptmr5 [r] h,w 11111111 11111111 pcsr5 [w] h,w xxxxxxxx xxxxxxxx ppg5 000298 h pdut5 [w] h,w xxxxxxxx xxxxxxxx pcn5 [r/w] b, h,w 0000000 - 000000 - 0 00029c h ptmr6 [r] h,w 11111111 11111111 pcsr6 [w] h,w xxxxxxxx xxxxxxxx ppg6 0002a0 h pdut6 [w] h,w xxxxxxxx xxxxxxxx pcn6 [r/w] b, h,w 0000000 - 000000 - 0 0002a4 h ptmr7 [r] h,w 11111111 11111111 pcsr7 [w] h,w xxxxxxxx xxxxxxxx ppg7 0002a8 h pdut7 [w] h,w xxxxxxxx xxxxxxxx pcn7 [r/w] b, h,w 0000000 - 000000 - 0 0002ac h ptmr8 [r] h,w 11111111 11111111 pcsr8 [w] h,w xxxxxxxx xxxxxxxx ppg8 0002b0 h pdut8 [w] h,w xxxxxxxx xxxxxxxx pcn8 [r/w] b, h,w 0000000 - 000000 - 0 0002b4 h ptmr9 [r] h,w 11111111 11111111 pcsr9 [w] h,w xxxxxxxx xxxxxxxx ppg9 0002b8 h pdut9 [w] h,w xxxxxxxx xxxxxxxx pcn9 [r/w] b, h,w 0000000 - 000000 - 0 0002bc h ptmr10 [r] h,w 11111111 11111111 pcsr10 [w] h,w xxxxxxxx xxxxxxxx ppg10 0002c0 h pdut10 [w] h,w xxxxxxxx xxxxxxxx pcn10 [r/w] b, h,w 0000000 - 000000 - 0 0002c4 h ipcp0 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx input capture 0,1 0002c8 h ipcp1 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0002cc h icfs01 [r/w] b, h, w ------ 00 D lsyns0 [r/w] b, h, w -- 000000 ics01 [r/w] b, h, w 00000000 document number: 002- 04727 rev. *b page 76 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 0002d0 h ipcp2 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx input capture 2,3 0002d4 h ipcp3 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0002d8 h icfs23 [r/w] b, h, w ------ 00 D D ics23 [r/w] b, h, w 00000000 0002dc h ipcp4 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx input capture 4,5 0002e0 h ipcp5 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0002e4 h icfs45 [r/w] b, h, w ------ 00 D D ics45 [r/w] b, h, w 00000000 0002e8 h occp0 [r/w] w 00000000 00000000 00000000 00000000 output compare 0,1 0002ec h occp1 [r/w] w 00000000 00000000 00000000 00000000 0002f0 h ocfs01 [r/w] b, h, w ------ 11 D ocsh01[r/w] b, h, w --- 0 -- 00 ocsl01[r/w] b, h, w 0000 -- 00 0002f4 h occp2 [r/w] w 00000000 00000000 00000000 00000000 output compare 2,3 0002f8 h occp3 [r/w] w 00000000 00000000 00000000 00000000 0002fc h ocfs23 [r/w] b, h, w ------ 11 D ocsh23[r/w] b, h, w --- 0 -- 00 ocsl23[r/w] b, h, w 0000 -- 00 000300 h to 00030c h D D D D reserved document number: 002- 04727 rev. *b page 77 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000310 h D D mpucr [r/w] h 000000 - 0 ---- 0100 mpu [s] (only the cpu can access this area) 000314 h D D D D D D D D D D dpvsr [r/w] h -------- 00000 -- 0 000328 h dear [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00032c h D D desr [r/w] h -------- 00000 -- 0 000330 h pabr0 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000334 h D D pacr0 [r/w] h 000000 - 0 00000 -- 0 000338 h pabr1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00033c h D D pacr1 [r/w] h 000000 - 0 00000 -- 0 000340 h pabr2 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000344 h D D pacr2 [r/w] h 000000 - 0 00000 -- 0 000348 h pabr3 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00034c h D D pacr3 [r/w] h 000000 - 0 00000 -- 0 000350 h pabr4 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 mpu [s] (only the cpu can access this area) 000354 h D D pacr4 [r/w] h 000000 - 0 00000 -- 0 000358 h pabr5 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00035c h D D pacr5 [r/w] h 000000 - 0 00000 -- 0 000360 h pabr6 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000364 h D D pacr6 [r/w] h 000000 - 0 00000 -- 0 000368 h pabr7 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00036c h D D pacr7 [r/w] h 000000 - 0 00000 -- 0 document number: 002- 04727 rev. *b page 78 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000370 h pabr8 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 mpu [s] ( only product mounting mpu 12ch or 16ch ) ( only the cpu can access this area ) 000374 h D D pacr8 [r/w] h 000000 - 0 00000 -- 0 000378 h pabr9[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00037c h D D pacr9 [r/w] h 000000 - 0 00000 -- 0 000380 h pabr10 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000384 h D D pacr10 [r/w] h 000000 - 0 00000 -- 0 000388 h pabr11 [r/w] ,w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00038c h D D pacr11 [r/w] h 000000 - 0 00000 -- 0 000390 h pabr12 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000394 h D D pacr12 [r/w] h 000000 - 0 00000 -- 0 000398 h pabr13 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00039c h D D pacr13 [r/w] h 000000 - 0 00000 -- 0 0003a0 h pabr14 [r/w]w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 0003a4 h D D pacr14 [r/w] h 000000 - 0 00000 -- 0 0003a8 h pabr15 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 0003ac h D D pacr15 [r/w] h 000000 - 0 00000 -- 0 0003b0 h to 0003fc h D D D D reserved [s] document number: 002- 04727 rev. *b page 79 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000400 h icsel0[r/w] b, h, w -----000 icsel1[r/w] b, h, w -----000 icsel2[r/w] b, h, w -------0 *1 ------ 00 *2 icsel3[r/w] b, h, w -------0 *1 ------ 00 *2 generation and clear of dma transfer request *1:mb91f591/2/4/6/7/9 *2:mb91f59a/b 000404 h icsel4[r/w] b, h, w ------- 0 icsel5[r/w] b, h, w ------- 0 icsel6[r/w] b, h, w ----- 000 icsel7[r/w] b, h, w ----- 000 000408 h icsel8[r/w] b, h, w ------00 icsel9[r/w] b, h, w ------00 *1 ----- 000 *2 icsel10[r/w] b, h, w ------00 *1 ----- 000 *2 icsel11[r/w] b, h, w ------00 00040c h icsel12[r/w] b, h, w ------00 icsel13[r/w] b, h, w -------0 icsel14[r/w] b, h, w -------0 icsel15[r/w] b, h, w -------- *1 ------- 0 *2 000410 h icsel16[r/w] b, h, w -------- *1 ------- 0 *2 icsel17[r/w] b, h, w -------- *1 ------- 0 *2 icsel18[r/w] b, h, w -------- *1 ------- 0 *2 icsel19[r/w] b, h, w -----000 000414 h icsel20[r/w] b, h, w ----- 000 icsel21[r/w] b, h, w ------ 00 icsel22[r/w] b, h, w ------ 00 D 000418 h irpr0h[r] b, h, w 00------ *1 0000 ---- *2 irpr0l[r] b, h, w 00------ *1 0000 ---- *2 irpr1h[r] b, h, w 00------ irpr1l[r] b, h, w 00------ interru pt request batch read register *1:mb91f591/2/4/6/7/9 *2:mb91f59a/b 00041c h irpr2h[r] b, h, w 00 ------ irpr2l[r] b, h, w 00 ------ irpr3h[r] b, h, w 000000 -- irpr3l[r] b, h, w 000000 -- 000420 h irpr4h[r] b, h, w 0000 ---- *1 00000 --- *2 irpr4l[r] b, h, w 0000 ---- *1 000000 -- *2 irpr5h[r] b, h, w 0000 ---- *1 00000 --- *2 irpr5l[r] b, h, w 0 ------- *1 000 ----- *2 000424 h irpr6h[r] b, h, w 00--0 --- *1 00000 --- *2 irpr6l[r] b, h, w 000----- *1 0000 ---- *2 irpr7h[r] b, h, w -00----- *1 - 0000 --- *2 irpr7l[r] b, h, w ------0 - *1 ------ 00 *2 000428 h irpr8h[r] b, h, w 00------ *1 0000 ---- *2 irpr8l[r] b, h, w 00------ *1 0000 ---- *2 irpr9h[r] b, h, w 00------ irpr9l[r] b, h, w 00------ 00042c h irpr10h[r] b, h, w 00 ------ irpr10l[r] b, h, w 00 ------ irpr11h[r] b, h, w 00 ------ irpr11l[r] b, h, w 00 ------ interru pt request batch read register mb91f59a/b only 000430 h irpr12h[r] b, h, w 00------ irpr12l[r] b, h, w 00------ irpr13h[r] b, h, w 000----- *1 00000 --- *2 irpr13l[r] b, h, w 00000 --- *1 0000000 - *2 interru pt request batch read register *1:mb91f591/2/4/6/7/9 *2:mb91f59a/b 000434 h irpr14h[r] b, h, w 00000000 irpr14l[r] b, h, w 00000000 irpr15h[r] b, h, w 000----- *1 0000 ---- *2 D 000438 h , 00043c h D D D D reserved document number: 002- 04727 rev. *b page 80 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000440 h icr00 [r/w] b, h, w --- 11111 icr01 [r/w] b, h, w --- 11111 icr02 [r/w] b, h, w --- 11111 icr03 [r/w] b, h, w --- 11111 interrupt controller [s] 000444 h icr04 [r/w] b, h, w --- 11111 icr05 [r/w] b, h, w --- 11111 icr06 [r/w] b, h, w --- 11111 icr07 [r/w] b, h, w --- 11111 000448 h icr08 [r/w] b, h, w --- 11111 icr09 [r/w] b, h, w --- 11111 icr10 [r/w] b, h, w --- 11111 icr11 [r/w] b, h, w --- 11111 00044c h icr12 [r/w] b, h, w --- 11111 icr13 [r/w] b, h, w --- 11111 icr14 [r/w] b, h, w --- 11111 icr15 [r/w] b, h, w --- 11111 000450 h icr16 [r/w] b, h, w --- 11111 icr17 [r/w] b, h, w --- 11111 icr18 [r/w] b, h, w --- 11111 icr19 [r/w] b, h, w --- 11111 000454 h icr20 [r/w] b, h, w --- 11111 icr21 [r/w] b, h, w --- 11111 icr22 [r/w] b, h, w --- 11111 icr23 [r/w] b, h, w --- 11111 000458 h icr24 [r/w] b, h, w --- 11111 icr25 [r/w] b, h, w --- 11111 icr26 [r/w] b, h, w --- 11111 icr27 [r/w] b, h, w --- 11111 00045c h icr28 [r/w] b, h, w --- 11111 icr29 [r/w] b, h, w --- 11111 icr30 [r/w] b, h, w --- 11111 icr31 [r/w] b, h, w --- 11111 000460 h icr32 [r/w] b, h, w --- 11111 icr33 [r/w] b, h, w --- 11111 icr34 [r/w] b, h, w --- 11111 icr35 [r/w] b, h, w --- 11111 000464 h icr36 [r/w] b, h, w --- 11111 icr37 [r/w] b, h, w --- 11111 icr38 [r/w] b, h, w --- 11111 icr39 [r/w] b, h, w --- 11111 000468 h icr40 [r/w] b, h, w --- 11111 icr41 [r/w] b, h, w --- 11111 icr42 [r/w] b, h, w --- 11111 icr43 [r/w] b, h, w --- 11111 00046c h icr44 [r/w] b, h, w --- 11111 icr45 [r/w] b, h, w --- 11111 icr46 [r/w] b, h, w --- 11111 icr47 [r/w] b, h, w --- 11111 000470 h to 00047c h D D D D reserved [s] 000480 h rstrr [r] b, h, w xxxx -- xx rstcr [r/w] b, h, w 111 ----0 stbcr [r/w] b, h, w *3 000---11 D reset control [s] power consumption control [s] *3: writing to stbcr by dma is disabled 000484 h D D D D D clock control [s] 00048c h D D D D document number: 002- 04727 rev. *b page 81 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000490 h iorr0[r/w] b, h, w - 0000000 iorr1[r/w] b, h, w - 0000000 iorr2[r/w] b, h, w - 0000000 iorr3[r/w] b, h, w - 0000000 dma transfer request from a peripheral [s] 000494 h iorr4[r/w] b, h, w - 0000000 iorr5[r/w] b, h, w - 0000000 iorr6[r/w] b, h, w - 0000000 iorr7[r/w] b, h, w - 0000000 000498 h iorr8[r/w] b, h, w - 0000000 iorr9[r/w] b, h, w - 0000000 iorr10[r/w] b, h, w - 0000000 iorr11[r/w] b, h, w - 0000000 00049c h iorr12[r/w] b, h, w - 0000000 iorr13[r/w] b, h, w - 0000000 iorr14[r/w] b, h, w - 0000000 iorr15[r/w] b, h, w - 0000000 0004a0 h D D D D D D D can prescaler 0004a8 h cpclr6 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 6 mb91f59a/b only 0004ac h tcdt6 [r/w] w 00000000 00000000 00000000 00000000 0004b0 h tccsh6 [r/w] b, h, w 0 ----- 00 tccsl6 [r/w] b, h, w - 1 - 00000 D 0004b4 h D D D D D D D D D D D rc trimming setting register 0004d0 h cpclr7 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 7 mb91f59a/b only 0004d4 h tcdt7 [r/w] w 00000000 00000000 00000000 00000000 0004d8 h tccsh7 [r/w] b, h, w 0 ----- 00 tccsl7 [r/w] b, h, w - 1 - 00000 D 0004dc h D D D D D D D D document number: 002- 04727 rev. *b page 82 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 0004f0 h scr9 [r/w] b,h,w 0 -- 00000 smr9 [r/w] b,h,w 000 - 0000 ssr9 [r/w] b,h,w 0 - 000011 escr9 [r/w] b,h,w - 0000000 multi - function serial 9 *1: byte access is possible only for access to lower 8 bits. mb91f59a/b only 0004f4 h rdr9/(tdr9)[r/w] b,h,w *1 ------- 0 00000000 bgr9 [r/w] h,w 00000000 00000000 0004f8 h D D D D D D D D reserved 000510 h cselr [r/w] b,h,w 001 --- 00 cmonr [r] b,h,w 001 --- 00 mtmcr [r/w] b,h,w 00001111 stmcr [r/w] b,h,w 0000 - 111 clock control [s] 000514 h pllcr [r/w] b,h,w -------- 11110000 cstbr [r/w] b,h,w - 0000000 ptmcr [r/w] b,h,w 00 ------ 000518 h D D cpuar [r/w] b,h,w 0 ---- xxx D reset [s] 00051c h D D D D D D ccpsdivr [r/w] b,h,w - 000 - 000 clock control 2 000524 h D ccpllfbr [r/w] b,h,w - 0000000 ccssfbr0 [r/w] b,h,w -- 000000 ccssfbr1 [r/w] b,h,w --- 00000 000528 h D ccssccr0 [r/w] b,h,w ---- 0000 ccssccr1 [r/w] h,w 000 ----- -------- clock control 2 00052c h D cccgrcr0 [r/w] b,h,w 00 ---- 00 cccgrcr1 [r/w] b,h,w 00000000 cccgrcr2 [r/w] b,h,w 00000000 000530 h ccrtselr [r/w] b,h,w 0 ------ 0 D ccpmucr0 [r/w] b,h,w 0 ----- 00 ccpmucr1 [r/w] b,h,w 0 -- 00000 000534 h D D D D D D D D D D D D D D D D reserved 000550 h eirr0 [r/w] b,h,w xxxxxxxx enir0 [r/w] b,h,w 00000000 elvr0 [r/w] b,h,w 00000000 00000000 external interrupt (int0 to int7) 000554 h eirr1 [r/w] b,h,w xxxxxxxx enir1 [r/w] b,h,w 00000000 elvr1 [r/w] b,h,w 00000000 00000000 external interrupt (int8 to int15) 000558 h D D D D document number: 002- 04727 rev. *b page 83 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 00055c h D D wtdr[r/w] h 00000000 00000000 real - time clock 000560 h D wtcrh [r/w] b ------ 00 wtcrm [r/w] b,h 00000000 wtcrl [r/w] b,h ---- 00 - 0 000564 h D wtbrh [r/w] b -- xxxxxx wtbrm [r/w] b xxxxxxxx wtbrl [r/w] b xxxxxxxx 000568 h wthr [r/w] b,h --- 00000 wtmr [r/w] b,h -- 000000 wtsr [r/w] b -- 000000 D 00056c h D csvcr [r/w] b - 001110- - 001010- *4 D D clock supervisor *4: an initial value is different by part number. for details, see the csvcr register in chapter "clock supervisor" 000570 h to 00057c h D D D D reserved 000580 h regsel [r/w] b,h,w 0110011 - D D D regulator control 000584 h lvd5r [r/w] b,h,w ------- 1 lvd5f [r/w] b,h,w 0 - 100 -- 1 lvd [r/w] b,h,w 01000 -- 0 D low - power detection 000588 h glvd5r[r/w] b,h,w 0 - 01 - 0 - x glvd5f[r/w] b,h,w 0 - 0100 - x glvd[r/w] b,h,w 010000 - x D 00058c h D D D D D pmu 000594 h pmuintf0 [r/w] b,h,w 00000000 pmuintf1 [r/w] b,h,w 00000000 pmuintf2 [r/w] b,h,w 0000 ---- D 000598 h gstr[r] b,h,w 0 ------- gctlr[r/w] b,h,w 0000 - 111 D D 00059c h D D D D D D D D reserved 000600 h to 00060c h D D D D reserved[s] 000610 h to 00063c h D D D D reserved[s] 000640 h to 00064c h D D D D reserved[s] 000650 h to 00067c h D D D D reserved[s] document number: 002- 04727 rev. *b page 84 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000680 h to 00068c h D D D D reserved[s] 000690 h to 0006bc h D D D D reserved[s] 0006c0 h to 0006cc h D D D D reserved[s] 0006d0 h to 0006f0 h D D D D reserved 0006f4 h D D D D D D D D reserved 000710 h bpccra[r/w] b 00000000 bpccrb[r/w] b 00000000 bpccrc[r/w] b 00000000 D bus performance cou nter 000714 h bpctra[r/w] w 00000000 00000000 00000000 00000000 000718 h bpctrb[r/w] w 00000000 00000000 00000000 00000000 00071c h bpctrc[r/w] w 00000000 00000000 00000000 00000000 000720 h to 0007f8 h D D D D reserved 0007fc h bmodr[r] b, h, w xxxxxxxx D D D operation mode 000800 h to 00083c h D D D D reserved [s] 000840 h fctlr[r/w] h - 0 -- 1000 0 -- 0 ---- D fstr[r/w] b ----- 001 flash memory register [s] 000844 h to 000854 h D D D D reserved [s] 000858 h D D wren[r/w] h 00000000 00000000 wild register [s ] 00085c h to 00087c h D D D D reserved [s] document number: 002- 04727 rev. *b page 85 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000880 h wrar00[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- wild register [ s] 000884 h wrdr00[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000888 h wrar01[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 00088c h wrdr01[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000890 h wrar02[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 000894 h wrdr02[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000898 h wrar03[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 00089c h wrdr03[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008a0 h wrar04[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- document number: 002- 04727 rev. *b page 86 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 0008a4 h wrdr04[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx wild register [ s] 0008a8 h wrar05[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008ac h wrdr05[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008b0 h wrar06[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008b4 h wrdr06[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008b8 h wrar07[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008bc h wrdr07[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008c0 h wrar08[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008c4 h wrdr08[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008c8 h wrar09[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008cc h wrdr09[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008d0 h wrar10[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008d4 h wrdr10[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008d8 h wrar11[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008dc h wrdr11[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008e0 h wrar12[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008e4 h wrdr12[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008e8 h wrar13[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008ec h wrdr13[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008f0 h wrar14[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008f4 h wrdr14[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008f8 h wrar15[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008fc h wrdr15[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000900 h to 000bf8 h D D D D reserved 000bfc h D D uer [w] b,h,w -------- ------- x ocdu document number: 002- 04727 rev. *b page 87 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000c00 h dccr0[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 dma controller [s] 000c04 h dcsr0[r/w] h 0 ------- ----- 000 dtcr0[r/w] h 00000000 00000000 000c08 h dsar0[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c0c h ddar0[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c10 h dccr1[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c14 h dcsr1[r/w] h 0 ------- ----- 000 dtcr1[r/w] h 00000000 00000000 000c18 h dsar1[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c1c h ddar1[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c20 h dccr2[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c24 h dcsr2[r/w] h 0 ------- ----- 000 dtcr2[r/w] h 00000000 00000000 000c28 h dsar2[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c2c h ddar2[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c30 h dccr3[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c34 h dcsr3[r/w] h 0 ------- ----- 000 dtcr3[r/w] h 00000000 00000000 000c38 h dsar3[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c3c h ddar3[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c40 h dccr4[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c44 h dcsr4[r/w] h 0 ------- ----- 000 dtcr4[r/w] h 00000000 00000000 000c48 h dsar4[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c4c h ddar4[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx document number: 002- 04727 rev. *b page 88 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000c50 h dccr5[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 dma controller [s] 000c54 h dcsr5[r/w] h 0 ------- ----- 000 dtcr5[r/w] h 00000000 00000000 000c58 h dsar5[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c5c h ddar5[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c60 h dccr6[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c64 h dcsr6[r/w] h 0 ------- ----- 000 dtcr6[r/w] h 00000000 00000000 000c68 h dsar6[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c6c h ddar6[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c70 h dccr7[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c74 h dcsr7[r/w] h 0 ------- ----- 000 dtcr7[r/w] h 00000000 00000000 000c78 h dsar7[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c7c h ddar7[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c80 h dccr8[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c84 h dcsr8[r/w] h 0 ------- ----- 000 dtcr8[r/w] h 00000000 00000000 000c88 h dsar8[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c8c h ddar8[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c90 h dccr9[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c94 h dcsr9[r/w] h 0 ------- ----- 000 dtcr9[r/w] h 00000000 00000000 000c98 h dsar9[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c9c h ddar9[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000ca0 h dccr10[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000ca4 h dcsr10[r/w] h 0 ------- ----- 000 dtcr10[r/w] h 00000000 00000000 000ca8 h dsar10[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx document number: 002- 04727 rev. *b page 89 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000cac h ddar10[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dma controller [s] 000cb0 h dccr11[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000cb4 h dcsr11[r/w] h 0 ------- ----- 000 dtcr11[r/w] h 00000000 00000000 000cb8 h dsar11[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cbc h ddar11[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cc0 h dccr12[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000cc4 h dcsr12[r/w] h 0 ------- ----- 000 dtcr12[r/w] h 00000000 00000000 000cc8 h dsar12[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000ccc h ddar12[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cd0 h dccr13[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000cd4 h dcsr13[r/w] h 0 ------- ----- 000 dtcr13[r/w] h 00000000 00000000 000cd8 h dsar13[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cdc h ddar13[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000ce0 h dccr14[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000ce4 h dcsr14[r/w] h 0 ------- ----- 000 dtcr14[r/w] h 00000000 00000000 000ce8 h dsar14[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cec h ddar14[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cf0 h dccr15[r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000cf4 h dcsr15[r/w] h 0 ------- ----- 000 dtcr15[r/w] h 00000000 00000000 000cf8 h dsar15[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cfc h ddar15[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000d00 h to 000df0 h D D D D reserved [s] 000df4 h D D dnmir[r/w] b 0 ------ 0 dilvr[r/w] b --- 11111 dma controller [s] 000df8 h dmacr[r/w] w 0 ------- -------- 0 ------- -------- 000dfc h D D D D document number: 002- 04727 rev. *b page 90 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000e00 h ddr00[r/w] b,h,w 00000000 ddr01[r/w] b,h,w 00000000 ddr02[r/w] b,h,w 00000000 ddr03[r/w] b,h,w 00000000 data direction register 000e04 h ddr04[r/w] b,h,w 00000000 ddr05[r/w] b,h,w 00000000 ddr06[r/w] b,h,w 00000000 ddr07[r/w] b,h,w 00000000 000e08 h ddr08[r/w] b,h,w 00000000 ddr09[r/w] b,h,w 00000000 ddr10[r/w] b,h,w 00000000 ddr11[r/w] b,h,w 00000000 000e0c h ddr12[r/w] b,h,w 00000000 ddr13[r/w] b,h,w 00 - 00000 D D 000e10 h ddra[r/w] b,h,w 000000 -- ddrb[r/w] b,h,w 000000 -- ddrc[r/w] b,h,w 000000 -- ddrd[r/w] b,h,w 000000 -- 000e14 h ddre[r/w] b,h,w 000000 -- ddrf[r/w] b,h,w 000000 -- ddrg[r/w] b,h,w 00000000 ddrh[r/w] b,h,w ---- 0 --- 000e18 h to 000e1c h D D D D reserved 000e20 h pfr00[r/w] b,h,w 00000000 pfr01[r/w] b,h,w 00000000 pfr02[r/w] b,h,w 00000000 pfr03[r/w] b,h,w 00000000 port function register 000e24 h pfr04[r/w] b,h,w 00000000 pfr05[r/w] b,h,w - 0000000 pfr06[r/w] b,h,w 00000000 pfr07[r/w] b,h,w 00000000 000e28 h pfr08[r/w] b,h,w 00000000 pfr09[r/w] b,h,w 0 - 000000 pfr10[r/w] b,h,w 00000000 pfr11[r/w] b,h,w 00000000 000e2c h pfr12[r/w] b,h,w 0 - 000000 pfr13[r/w] b,h,w --- 00000 D D 000e30 h pfra[r/w] b,h,w -------- pfrb[r/w] b,h,w -------- pfrc[r/w] b,h,w -------- pfrd[r/w] b,h,w 000000 -- 000e34 h pfre[r/w] b,h,w 000000 -- pfrf[r/w] b,h,w 000000 -- pfrg[r/w] b,h,w 00000 --- pfrh[r/w] b,h,w -------- 000e38 h to 000e3c h D D D D reserved document number: 002- 04727 rev. *b page 91 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000e40 h pddr00[r] b,h,w xxxxxxxx pddr01[r] b,h,w xxxxxxxx pddr02[r] b,h,w xxxxxxxx pddr03[r] b,h,w xxxxxxxx input data direct read register 000e44 h pddr04[r] b,h,w xxxxxxxx pddr05[r] b,h,w xxxxxxxx pddr06[r] b,h,w xxxxxxxx pddr07[r] b,h,w xxxxxxxx 000e48 h pddr08[r] b,h,w xxxxxxxx pddr09[r] b,h,w xxxxxxxx pddr10[r] b,h,w xxxxxxxx pddr11[r] b,h,w xxxxxxxx 000e4c h pddr12[r] b,h,w xxxxxxxx pddr13[r] b,h,w xx - xxxxx D D 000e50 h pddra[r] b,h,w xxxxxx -- pddrb[r] b,h,w xxxxxx -- pddrc[r] b,h,w xxxxxx -- pddrd[r] b,h,w xxxxxx -- 000e54 h pddre[r] b,h,w xxxxxx -- pddrf[r] b,h,w xxxxxx -- pddrg[r] b,h,w xxxxxxxx pddrh[r] b,h,w ---- x --- 000e58 h to 000e5c h D D D D reserved document number: 002- 04727 rev. *b page 92 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000e60 h epfr00[r/w] b,h,w 00000000 epfr01[r/w] b,h,w ----0000 *1 00000000 *2 epfr02[r/w] b,h,w --- 00000 epfr03[r/w] b,h,w --- 00000 extended port function register *1:mb91f591/2/4/6/7/9 *2:mb91f59a/b 000e64 h epfr04[r/w] b,h,w --- 00000 epfr05[r/w] b,h,w --- 00000 epfr06[r/w] b,h,w --- 00000 epfr07[r/w] b,h,w --- 00000 000e68 h epfr08[r/w] b,h,w --- 00000 epfr09[r/w] b,h,w --- 00000 epfr10[r/w] b,h,w - 0000000 epfr11[r/w] b,h,w -- 000000 000e6c h epfr12[r/w] b,h,w -- 000000 epfr13[r/w] b,h,w -- 000000 epfr14[r/w] b,h,w -- 000000 epfr15[r/w] b,h,w - 0000000 000e70 h epfr16[r/w] b,h,w 00000000 epfr17[r/w] b,h,w 00000000 epfr18[r/w] b,h,w 10000000 epfr19[r/w] b,h,w 11111111 000e74 h epfr20[r/w] b,h,w - 1111111 epfr21[r/w] b,h,w 00000000 epfr22[r/w] b,h,w 00000000 epfr23[r/w] b,h,w 00000000 000e78 h epfr24[r/w] b,h,w ----- 000 epfr25[r/w] b,h,w ----- 000 epfr26[r/w] b,h,w ---- 0000 epfr27[r/w] b,h,w --- 00000 000e7c h epfr28[r/w] b,h,w ------ 00 epfr29[r/w] b,h,w 00000000 epfr30[r/w] b,h,w 00000000 epfr31[r/w] b,h,w 00000000 000e80 h epfr32[r/w] b,h,w 00000000 epfr33[r/w] b,h,w --- 00000 epfr34[r/w] b,h,w --- 00000 epfr35[r/w] b,h,w --- 00000 000e84 h epfr36[r/w] b,h,w --- 00000 epfr37[r/w] b,h,w 00000000 epfr38[r/w] b,h,w --- 00000 epfr39[r/w] b,h,w 00000000 000e88 h epfr40[r/w] b,h,w -- 000000 epfr41[r/w] b,h,w ----- 000 epfr42[r/w] b,h,w ------ 00 epfr43[r/w] b,h,w 00000000 000e8c h epfr44[r/w] b,h,w 00000000 epfr45[r/w] b,h,w 00000000 epfr46[r/w] b,h,w -- 000000 epfr47[r/w] b,h,w ------- 0 000e90 h epfr48[r/w] b,h,w 00000000 epfr49[r/w] b,h,w 00000000 epfr50[r/w] b,h,w 00000000 epfr51[r/w] b,h,w --- 00000 000e94 h epfr52[r/w] b,h,w ----- 000 epfr53[r/w] b,h,w --- 00000 epfr54[r/w] b,h,w ---- 0000 epfr55[r/w] b,h,w ------ 01 000e98 h epfr56[r/w] b,h,w -- 000000 epfr57[r/w] b,h,w -- 000000 epfr58[r/w] b,h,w ---- 0000 D extended port function register mb91f59a/b only 000e9c h D D D D document number: 002- 04727 rev. *b page 93 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000ea0 h ppcr00[r/w] b,h,w 11111111 ppcr01[r/w] b,h,w 11111111 ppcr02[r/w] b,h,w 11111111 ppcr03[r/w] b,h,w 11111111 port pull - up/down control register 000ea4 h ppcr04[r/w] b,h,w 11111111 ppcr05[r/w] b,h,w 11111111 ppcr06[r/w] b,h,w 11111111 ppcr07[r/w] b,h,w 11111111 000ea8 h ppcr08[r/w] b,h,w 11111111 ppcr09[r/w] b,h,w 11111111 ppcr10[r/w] b,h,w 11111111 ppcr11[r/w] b,h,w 11111111 000eac h ppcr12[r/w] b,h,w 11111111 ppcr13[r/w] b,h,w 11 - 11111 D D 000eb0 h ppcra[r/w] b,h,w 111111 -- ppcrb[r/w] b,h,w 111111 -- ppcrc[r/w] b,h,w 111111 -- ppcrd[r/w] b,h,w 111111 -- 000eb4 h ppcre[r/w] b,h,w 111111 -- ppcrf[r/w] b,h,w 111111 -- ppcrg[r/w] b,h,w 11111111 ppcrh[r/w] b,h,w ---- 1 --- 000eb8 h to 000ebc h D D D D reserved 000ec0 h pper00[r/w] b,h,w 00000000 pper01[r/w] b,h,w 00000000 pper02[r/w] b,h,w 00000000 pper03[r/w] b,h,w 00000000 port pull - up/down enable register 000ec4 h pper04[r/w] b,h,w 00000000 pper05[r/w] b,h,w 00000000 pper06[r/w] b,h,w 00000000 pper07[r/w] b,h,w 00000000 000ec8 h pper08[r/w] b,h,w 00000000 pper09[r/w] b,h,w 00000000 pper10[r/w] b,h,w 00000000 pper11[r/w] b,h,w 00000000 000ecc h pper12[r/w] b,h,w 00000000 pper13[r/w] b,h,w 00 - 00000 D D 000ed0 h ppera[r/w] b,h,w 000000 -- pperb[r/w] b,h,w 000000 -- pperc[r/w] b,h,w 000000 -- pperd[r/w] b,h,w 000000 -- 000ed4 h ppere[r/w] b,h,w 000000 -- pperf[r/w] b,h,w 000000 -- pperg[r/w] b,h,w 00000000 pperh[r/w] b,h,w ---- 0 --- 000ed8 h to 000edc h D D D D reserved document number: 002- 04727 rev. *b page 94 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000ee0 h pilr00[r/w] b,h,w 11111111 pilr01[r/w] b,h,w 11111111 pilr02[r/w] b,h,w 11111111 pilr03[r/w] b,h,w 11111111 port input level selection register 000ee4 h pilr04[r/w] b,h,w 11111111 pilr05[r/w] b,h,w 11111111 pilr06[r/w] b,h,w 11111111 pilr07[r/w] b,h,w 11111111 000ee8 h pilr08[r/w] b,h,w 11111111 pilr09[r/w] b,h,w 11111111 pilr10[r/w] b,h,w 11111111 pilr11[r/w] b,h,w 11111111 000eec h pilr12[r/w] b,h,w 11111111 pilr13[r/w] b,h,w 11 - 11111 D D 000ef0 h pilra[r/w] b,h,w 111111 -- pilrb[r/w] b,h,w 111111 -- pilrc[r/w] b,h,w 111111 -- pilrd[r/w] b,h,w 111111 -- 000ef4 h pilre[r/w] b,h,w 111111 -- pilrf[r/w] b,h,w 111111 -- pilrg[r/w] b,h,w 11111111 pilrh[r/w] b,h,w ---- 1 --- 000ef8 h to 000efc h D D D D reserved 000f00 h D D D D D D epilr06[r/w] b,h,w 00000000 epilr07[r/w] b,h,w 00000000 000f08 h epilr08[r/w] b,h,w 00000000 epilr09[r/w] b,h,w 00000000 epilr10[r/w] b,h,w 00000000 epilr11[r/w] b,h,w 00000000 000f0c h epilr12[r/w] b,h,w 00000000 epilr13[r/w] b,h,w 00 - 00000 D D 000f10 h D D D D D D D D D D D D reserved 000f20 h D D D D D D podr06[r/w] b,h,w 00000000 podr07[r/w] b,h,w 00000000 000f28 h podr08[r/w] b,h,w 00000000 podr09[r/w] b,h,w 00000000 podr10[r/w] b,h,w 00000000 podr11[r/w] b,h,w 00000000 000f2c h podr12[r/w] b,h,w 00000000 podr13[r/w] b,h,w 00 - 00000 D D 000f30 h D D D D D D D D D extended port output drive register 000f3c h epodrgd [r/w]b,h,w ---- 1010 epodrgf [r/w]b,h,w -- 101010 D D document number: 002- 04727 rev. *b page 95 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000f40 h porten [r/w] b,h,w ------- 0 D D D port input enable register 000f44 h to 000f4c h D D D D reserved 000f50 h D gpllcr[r/w] b,h,w 0 ------ 0 ptimcr[r/w] b,h,w ---- 1111 pedivcr[r/w] b,h,w - 000 - 000 gdc control register 000f54 h D pdivcr[r/w] b,h,w - 0000000 sdivcr0[r/w] b,h,w -- 000000 sdivcr1[r/w] b,h,w --- 00000 000f58 h D ssscr0[r/w] b,h,w ---- 0000 ssscr1[r/w] h,w 000 ----- -------- 000f5c h D pgrcr0[r/w] b,h,w 00 ---- 00 pgrcr1[r/w] b,h,w 00000000 pgrcr2[r/w] b,h,w 00000000 000f60 h D sgrcr0[r/w] b,h,w 00 ---- 00 sgrcr1[r/w] b,h,w 00000000 sgrcr2[r/w] b,h,w 00000000 000f64 h D gdccr[r/w] b,h,w -- 000001 gdctrgr [r/w] b,h,w 0000 -- 00 gdcswpr [r/w] b,h,w --- 00101 000f68 h to 000f6c h D D D D reserved 000f70 h rcrh0[w] h,w xxxxxxxx rcrl0[w] b,h,w xxxxxxxx udcrh0[r] h,w 00000000 udcrl0[r] b,h,w 00000000 up/down counter 0 mb91f59a/b only 000f74 h ccr0[r/w] b,h 00000000 - 0001000 D csr0[r/w] b 00000000 000f78 h to 000f7c h D D D D reserved 000f80 h rcrh1[w] h,w xxxxxxxx rcrl1[w] b,h,w xxxxxxxx udcrh1[r] h,w 00000000 udcrl1[r] b,h,w 00000000 up/down counter 1 mb91f59a/b only 000f84 h ccr1[r/w] b,h 00000000 - 0001000 D csr1[r/w] b 00000000 000f88 h to 000f9c h D D D D reserved 000fa0 h cpclr2 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 2 000fa4 h tcdt2 [r/w] w 00000000 00000000 00000000 00000000 000fa8 h tccsh2 [r/w] b, h, w 0 ----- 00 tccsl2 [r/w] b, h, w - 1 - 00000 D document number: 002- 04727 rev. *b page 96 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 000fac h cpclr3 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 3 000fb0 h tcdt3 [r/w] w 00000000 00000000 00000000 00000000 000fb4 h tccsh3 [r/w] b, h, w 0 ----- 00 tccsl3 [r/w] b, h, w - 1 - 00000 D 000fb8 h cpclr4 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 4 mb91f59a/b only 000fbc h tcdt4 [r/w] w 00000000 00000000 00000000 00000000 000fc0 h tccsh4 [r/w] b, h, w 0 ----- 00 tccsl4 [r/w] b, h, w - 1 - 00000 D 000fc4 h cpclr5 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 5 mb91f59a/b only 000fc8 h tcdt5 [r/w] w 00000000 00000000 00000000 00000000 000fcc h tccsh5 [r/w] b, h, w 0 ----- 00 tccsl5 [r/w] b, h, w - 1 - 00000 D 000fd0 h ipcp6 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx input capture 6,7 *1:mb91f591/2/4/6/7/9 *2:mb91f59a/b 000fd4 h ipcp7 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000fd8 h icfs67 [r/w] b, h, w ------00 D lsyns1 [r/w] b,h,w ------00 *1 -- 000000 *2 ics67 [r/w] b, h, w 00000000 000fdc h ipcp8 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx input capture 8,9 mb91f59a/b only 000fe0 h ipcp9 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000fe4 h icfs89 [r/w] b, h, w ------ 00 D D ics89 [r/w] b, h, w 00000000 000fe8 h ipcp10 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx input capture 10,11 mb91f59a/b only 000fec h ipcp11 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000ff0 h icfs1011 [r/w] b, h, w ------ 00 D D ics1011 [r/w] b, h, w 00000000 000ff4 h rcrh2[w] h,w xxxxxxxx rcrl2[w] b,h,w xxxxxxxx udcrh2[r] h,w 00000000 udcrl2[r] b,h,w 00000000 up/down counter 2 mb91f59a/b only 000ff8 h ccr2[r/w] b,h 00000000 - 0001000 D csr2[r/w] b 00000000 000ffc h D D D D D D synchronous/asynchronous switching control 001004 h to 00103c h D D D D reserved document number: 002- 04727 rev. *b page 97 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 001040 h D sgder0[r/w] b,h,w 00000000 sgcr0[r/w] b,h,w - 0000-0 - 000 -- 000 sound generator 0 001044 h sgar0[r/w] b,h,w 00000000 00000000 sgfr0[r/w] b,h,w 00000000 sgnr0[r/w] b,h,w 00000000 001048 h sgtcr0[r/w] b,h,w 00000000 sgidr0[r/w] b,h,w 00000000 sgpcr0[r/w] b,h,w 00000000 11111111 00104c h sgdmar0[w] b,h,w 00000000 00000000 00000000 00000000 001050 h to 00105c h D D D D reserved 001060 h D sgder1[r/w] b,h,w 00000000 sgcr1[r/w] b,h,w - 0000-0 - 000 -- 000 sound generator 1 001064 h sgar1[r/w] b,h,w 00000000 00000000 sgfr1[r/w] b,h,w 00000000 sgnr1[r/w] b,h,w 00000000 001068 h sgtcr1[r/w] b,h,w 00000000 sgidr1[r/w] b,h,w 00000000 sgpcr1[r/w] b,h,w 00000000 11111111 00106c h sgdmar1[w] b,h,w 00000000 00000000 00000000 00000000 001070 h to 00107c h D D D D reserved 001080 h D sgder2[r/w] b,h,w 00000000 sgcr2[r/w] b,h,w - 0000-0 - 000 -- 000 sound generator 2 001084 h sgar2[r/w] b,h,w 00000000 00000000 sgfr2[r/w] b,h,w 00000000 sgnr2[r/w] b,h,w 00000000 001088 h sgtcr2[r/w] b,h,w 00000000 sgidr2[r/w] b,h,w 00000000 sgpcr2[r/w] b,h,w 00000000 11111111 00108c h sgdmar2[w] b,h,w 00000000 00000000 00000000 00000000 001090 h to 00109c h D D D D reserved 0010a0 h D sgder3[r/w] b,h,w 00000000 sgcr3[r/w] b,h,w - 0000-0 - 000 -- 000 sound generator 3 0010a4 h sgar3[r/w] b,h,w 00000000 00000000 sgfr3[r/w] b,h,w 00000000 sgnr3[r/w] b,h,w 00000000 0010a8 h sgtcr3[r/w] b,h,w 00000000 sgidr3[r/w] b,h,w 00000000 sgpcr3[r/w] b,h,w 00000000 11111111 0010ac h sgdmar3[w] b,h,w 00000000 00000000 00000000 00000000 0010b0 h to 0010bc h D D D D reserved document number: 002- 04727 rev. *b page 98 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 0010c0 h D sgder4[r/w] b,h,w 00000000 sgcr4[r/w] b,h,w - 0000-0 - 000 -- 000 sound generator 4 0010c4 h sgar4[r/w] b,h,w 00000000 00000000 sgfr4[r/w] b,h,w 00000000 sgnr4[r/w] b,h,w 00000000 0010c8 h sgtcr4[r/w] b,h,w 00000000 sgidr4[r/w] b,h,w 00000000 sgpcr4[r/w] b,h,w 00000000 11111111 0010cc h sgdmar4[w] b,h,w 00000000 00000000 00000000 00000000 0010d0 h to 00112c h D D D D reserved 001130 h D D D crccr[r/w] b,h,w - 0000000 c rc arithmetic operation 001134 h crcinit[r/w] b,h,w 1111111 1111111 1111111 1111111 001138 h crcin[r/w] b,h,w 00000000 00000000 00000000 00000000 00113c h crcr[r] b,h,w 1111111 1111111 1111111 1111111 001140 h to 0013fc h D D D D reserved 001400 h to 001ffc h D D D D reserved (3kb) document number: 002- 04727 rev. *b page 99 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 002000 h ctrlr0 [r/w] b,h,w -------- 000 - 0001 statr0[r/w] b,h,w -------- 00000000 can0 (64msg) 002004 h errcnt0 [r] b,h,w 00000000 00000000 btr0[r/w] b,h,w - 0100011 00000001 002008 h intr0 [r] b,h,w 00000000 00000000 testr0[r/w] b,h,w -------- x00000 -- 00200c h brper0 [r/w] b,h,w -------- ---- 0000 D 002010 h if1creq0 [r/w] b,h,w 0 ------- 00000001 if1cmsk0 [r/w] b,h,w -------- 00000000 002014 h if1msk20 [r/w] b,h,w 11 - 11111 11111111 if1msk10 [r/w] b,h,w 11111111 11111111 002018 h if1arb20 [r/w] b,h,w 00000000 00000000 if1arb10 [r/w] b,h,w 00000000 00000000 00201c h if1mctr0 [r/w] b,h,w 00000000 0 --- 0000 D 002020 h if1dta10 [r/w] b,h,w 00000000 00000000 if1dta20[r/w] b,h,w 00000000 00000000 002024 h if1dtb10 [r/w] b,h,w 00000000 00000000 if1dtb20 [r/w] b,h,w 00000000 00000000 002028 h , 00202c h reserved 002030 h , 002034 h reserved (if1 data mirror) 002038 h , 00203c h reserved 002040 h if2creq0 [r/w] b,h,w 0 ------- 00000001 if2cmsk0 [r/w] b,h,w -------- 00000000 002044 h if2msk20 [r/w] b,h,w 11 - 11111 11111111 if2msk10 [r/w] b,h,w 11111111 11111111 002048 h if2arb20 [r/w] b,h,w 00000000 00000000 if2arb10 [r/w] b,h,w 00000000 00000000 00204c h if2mctr0 [r/w] b,h,w 00000000 0 --- 0000 D document number: 002- 04727 rev. *b page 100 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 002050 h if2dta10 [r/w] b,h,w 00000000 00000000 if2dta20 [r/w] b,h,w 00000000 00000000 can0 (64msg) 002054 h if2dtb10 [r/w] b,h,w 00000000 00000000 if2dtb20 [r/w] b,h,w 00000000 00000000 002058 h , 00205c h reserved 002060 h , 002064 h reserved (if2 data mirror) 002068 h to 00207c h reserved 002080 h treqr20 [r] b,h,w 00000000 00000000 treqr10 [r] b,h,w 00000000 00000000 002084 h treqr40 [r] b,h,w 00000000 00000000 treqr30 [r] b,h,w 00000000 00000000 002088 h D D D D D D D D D D D D D D D D document number: 002- 04727 rev. *b page 101 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 002100 h ctrlr1 [r/w] b,h,w -------- 000 - 0001 statr1[r/w] b,h,w -------- 00000000 can1 (32msg) 002104 h errcnt1 [r] b,h,w 00000000 00000000 btr1[r/w] b,h,w - 0100011 00000001 002108 h intr1 [r] b,h,w 00000000 00000000 testr1[r/w] b,h,w -------- x00000 -- 00210c h brper1 [r/w] b,h,w -------- ---- 0000 D 002110 h if1creq1 [r/w] b,h,w 0 ------- 00000001 if1cmsk1 [r/w] b,h,w -------- 00000000 002114 h if1msk21 [r/w] b,h,w 11 - 11111 11111111 if1msk11 [r/w] b,h,w 11111111 11111111 002118 h if1arb21 [r/w] b,h,w 00000000 00000000 if1arb11 [r/w] b,h,w 00000000 00000000 00211c h if1mctr1 [r/w] b,h,w 00000000 0 --- 0000 D 002120 h if1dta11 [r/w] b,h,w 00000000 00000000 if1dta21 [r/w] b,h,w 00000000 00000000 002124 h if1dtb11 [r/w] b,h,w 00000000 00000000 if1dtb21 [r/w] b,h,w 00000000 00000000 002128 h , 00212c h reserved 002130 h , 002134 h reserved (if1 data mirror) 002138 h , 00213c h reserved 002140 h if2creq1 [r/w] b,h,w 0 ------- 00000001 if2cmsk1 [r/w] b,h,w -------- 00000000 002144 h if2msk21 [r/w] b,h,w 11 - 11111 11111111 if2msk11 [r/w] b,h,w 11111111 11111111 002148 h if2arb21 [r/w] b,h,w 00000000 00000000 if2arb11 [r/w] b,h,w 00000000 00000000 document number: 002- 04727 rev. *b page 102 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 00214c h if2mctr1 [r/w] b,h,w 00000000 0 --- 0000 D can1 (32msg) 002150 h if2dta11 [r/w] b,h,w 00000000 00000000 if2dta21 [r/w] b,h,w 00000000 00000000 002154 h if2dtb11 [r/w] b,h,w 00000000 00000000 if2dtb21 [r/w] b,h,w 00000000 00000000 002158 h , 00215c h reserved 002160 h , 002164 h reserved (if2 data mirror) 002168 h to 00217c h reserved 002180 h treqr21 [r] b,h,w 00000000 00000000 treqr11 [r] b,h,w 00000000 00000000 002184 h D D D D D D D D D D D D D D D D D D D D D D D D document number: 002- 04727 rev. *b page 103 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 002200 h ctrlr2 [r/w] b,h,w -------- 000 - 0001 statr2[r/w] b,h,w -------- 00000000 can2 (32msg) 002204 h errcnt2[r] b,h,w 00000000 00000000 btr2[r/w] b,h,w - 0100011 00000001 002208 h intr2[r] b,h,w 00000000 00000000 testr2[r/w] b,h,w -------- x00000 -- 00220c h brper2 [r/w] b,h,w -------- ---- 0000 D 002210 h if1creq2[r/w] b,h,w 0 ------- 00000001 if1cmsk2[r/w] b,h,w -------- 00000000 002214 h if1msk22 [r/w] b,h,w 11 - 11111 11111111 if1msk12 [r/w] b,h,w 11111111 11111111 002218 h if1arb22 [r/w] b,h,w 00000000 00000000 if1arb12 [r/w] b,h,w 00000000 00000000 00221c h if1mctr2[r/w] b,h,w 00000000 0 --- 0000 D 002220 h if1dta12 [r/w] b,h,w 00000000 00000000 if1dta22 [r/w] b,h,w 00000000 00000000 002224 h if1dtb12 [r/w] b,h,w 00000000 00000000 if1dtb22 [r/w] b,h,w 00000000 00000000 002228 h , 00222c h reserved 002230 h , 002234 h reserved (if1 data mirror) 002238 h , 00223c h reserved 002240 h if2creq2[r/w] b,h,w 0 ------- 00000001 if2cmsk2[r/w] b,h,w -------- 00000000 002244 h if2msk22 [r/w] b,h,w 11 - 11111 11111111 if2msk12[r/w] b,h,w 11111111 11111111 002248 h if2arb22[r/w] b,h,w 00000000 00000000 if2arb12[r/w] b,h,w 00000000 00000000 00224c h if2mctr2[r/w] b,h,w 00000000 0 --- 0000 D 002250 h if2dta12[r/w] b,h,w 00000000 00000000 if2dta22[r/w] b,h,w 00000000 00000000 002254 h if2dtb12[r/w] b,h,w 00000000 00000000 if2dtb22[r/w] b,h,w 00000000 00000000 document number: 002- 04727 rev. *b page 104 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 002258 h , 00225c h reserved can2 (32msg) 002260 h , 002264 h reserved (if2 data mirror) 002268 h to 00227c h reserved 002280 h treqr22[r] b,h,w 00000000 00000000 treqr12[r] b,h,w 00000000 00000000 002284 h D D D D D D D D D D D D D D D D D D D D D D D D D D D D reserved 002300 h dfctlr[r/w]b,h,w -0 ------ -------- D dfstr [r/w] b,h,w ----- 001 workflash 002304 h D D D D D fliffer1 [r/w] b,h,w -------- fliffer2 [r/w] b,h,w -------- 00230c h to 0023fc h D D D D reserved 002400 h seearx[r] b,h,w 00000000 00000000 deearx[r] b,h,w 00000000 00000000 xbs ram ecc control register 002404 h eecsrx [r/w] b,h,w ---- 0000 D efearx[r/w] b,h,w 00000000 00000000 002408 h D efecrx[r/w] b,h,w ------- 0 00000000 00000000 00240c h to 0024fc h D D D D reserved document number: 002- 04727 rev. *b page 105 of 174 mb91590 series address address offset value / register name block +0 +1 +2 +3 002500 h seearh[r] b,h,w -- 000000 00000000 deearh[r] b,h,w -- 000000 00000000 ahb ram ecc control register mb91f59a/b only 002504 h eecsrh[r/w] b,h,w ---- 0000 D efearh[r/w]b,h,w -- 000000 00000000 002508 h D efecrh[r/w]b,h,w ------- 0 00000000 00000000 00250c h to 002ffc h D D D D reserved 003000 h seeara[r] b,h,w ----- 000 00000000 deeara[r] b,h,w ----- 000 00000000 backup ram ecc control register 003004 h eecsra [r/w] b,h,w ---- 0000 D efeara[r/w] b,h,w ----- 000 00000000 003008 h D efecra[r/w] b,h,w ------- 0 00000000 00000000 00300c h to 003ffc h D D D D reserved 004000 h to 005ffc h backup ram backup ram area 006000 h to 00effc h D D D D reserved 00f000 h to 00fefc h D D D D reserved [s] 00ff00 h dsucr [r/w] b,h,w -------- ------- 0 D D ocdu [s] 00ff04 h to 00ff0c h D D D D reserved [s] 00ff10 h pcsr [r/w] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ocdu [s] 00ff14 h pssr [r/w] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00ff18 h to 00fff4 h D D D D reserved [s] 00fff8 h edir1 [r] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ocdu [s] 00fffc h edir0 [r] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx [s]: it is a system register. the illegal instruction exception (data access error) is generated in these registers in the user mo de when reading and writing to it. document number: 002- 04727 rev. *b page 106 of 174 mb91590 series 10. interrupt vector table this list shows the assignments of interrupt factors and interrupt vectors/interrupt control registers. ? interrupt vector interrupt factor interrupt number interrupt level offset default address for tbr rn *1 decimal hexa - decimal reset 0 00 - 3fc h 000ffffc h - system reserved 1 01 - 3f8 h 000ffff8 h - system reserved 2 02 - 3f4 h 000ffff4 h - system reserved 3 03 - 3f0 h 000ffff0 h - system reserved 4 04 - 3ec h 000fffec h - fpu exception 5 05 - 3e8 h 000fffe8 h - exception of instruction access protection violation 6 06 - 3e4 h 000fffe4 h - exception of data access protection violation 7 07 - 3e0 h 000fffe0 h - data access error interrupt 8 08 - 3dc h 000fffdc h - inte instruction 9 09 - 3d8 h 000fffd8 h - instruction break 10 0a - 3d4 h 000fffd4 h - system reserved 11 0b - 3d0 h 000fffd0 h - system reserved 12 0c - 3cc h 000fffcc h - system reserved 13 0d - 3c8 h 000fffc8 h - exception of invalid instruction 14 0e - 3c4 h 000fffc4 h - nmi request / xbs ram double - bit error generation/ ahb ram double - bit error generation ** / backup ram double - bit error generation 15 0f 15 (f h ) fixed 3c0 h 000fffc0 h - external interrupt 0 - 7 16 10 icr00 3bc h 000fffbc h 0 external interrupt 8 - 15 17 11 icr01 3b8 h 000fffb8 h 1 reload timer 0/1/7 ** /8 ** 18 12 icr02 3b4 h 000fffb4 h 2 reload timer 2/3/9 ** /10 ** 19 13 icr03 3b0 h 000fffb0 h 3 multi - function serial interface ch.0 ( reception completed)/ multi - function serial interface ch.0(status) 20 14 icr04 3ac h 000fffac h 4* 2 multi - function serial interface ch.0 ( transmission completed ) 21 15 icr05 3a8 h 000fffa8 h 5 multi - function serial interface ch.1 ( reception completed)/ multi - function serial interface ch.1(status) 22 16 icr06 3a4 h 000fffa4 h 6* 2 multi - function serial interface ch.1 ( transmission completed ) 23 17 icr07 3a0 h 000fffa0 h 7 lin - uart2( reception completed ) 24 18 icr08 39c h 000fff9c h 8 lin - uart2( transmission completed ) 25 19 icr09 398 h 000fff98 h 9 lin - uart3( reception completed ) 26 1a icr10 394 h 000fff94 h 10 lin - uart3(transmission completed) 27 1b icr11 390 h 000fff90 h 11 lin - uart4(reception completed) 28 1c icr12 38c h 000fff8c h 12 lin - uart4(transmission completed) 29 1d icr13 388 h 000fff88 h 13 lin - uart5(reception completed) 30 1e icr14 384 h 000fff84 h 14 lin - uart5(transmission completed) 31 1f icr15 380 h 000fff80 h 15 lin - uart6(reception completed) 32 20 icr16 37c h 000fff7c h 16 lin - uart6(transmission completed) 33 21 icr17 378 h 000fff78 h 17 can0 34 22 icr18 374 h 000fff74 h - can1 35 23 icr19 370 h 000fff70 h - can2/udc0 ** /1 ** 36 24 icr20 36c h 000fff6c h - real time clock 37 25 icr21 368 h 000fff68 h - document number: 002- 04727 rev. *b page 107 of 174 mb91590 series interrupt factor interrupt number interrupt level offset default address for tbr rn *1 decimal hexa - decimal sound generator 0 / lin - uart7 (reception completed) 38 26 icr22 364 h 000fff64 h 22 sound generator 1 / lin - uart7 (transmission completed) 39 27 icr23 360 h 000fff60 h 23 ppg0/1/10/11/20/21 40 28 icr24 35c h 000fff5c h 24 ppg2/3/12/13/22/23 41 29 icr25 358 h 000fff58 h 25 ppg4/5/14/15/udc2 ** 42 2a icr26 354 h 000fff54 h 26 *6 ppg6/7/16/17/ multi - function serial interface ch.10 ( reception completed ) ** / multi - function serial interface ch.10(status) ** 43 2b icr27 350 h 000fff50 h 27 ppg8/9/18/19/ multi - function serial interface ch.10 ( transmission completed ) ** 44 2c icr28 34c h 000fff4c h 28 gdc/gdc_alm/gdc_lvd/ multi - function serial interface ch.8 ( reception completed ) ** / multi - function serial interface ch.8(status) ** 45 2d icr29 348 h 000fff48 h 29 *7 main timer/sub timer/pll timer/ multi - function serial interface ch.8 ( transmission completed ) ** 46 2e icr30 344 h 000fff44 h 30 clock calibration unit (sub oscillation) / sound generator 4/ multi - function serial interface ch.9 ( reception c ompleted ) ** / multi - function serial interface ch.9(status) ** 47 2f icr31 340 h 000fff40 h 31* 3 a/d converter 48 30 icr32 33c h 000fff3c h 32 clock calibration unit (cr oscillation) / multi - function serial interface ch.9 ( transmission completed ) ** 49 31 icr33 338 h 000fff38 h 33* 3 free - run timer 0/2/4 ** /6 ** 50 32 icr34 334 h 000fff34 h - free - run timer 1/3/5 ** /7 ** 51 33 icr35 330 h 000fff30 h - icu0/6(fetching) 52 34 icr36 32c h 000fff2c h 36 icu1/7(fetching) 53 35 icr37 328 h 000fff28 h 37 icu2/8 ** (fetching) 54 36 icr38 324 h 000fff24 h 38 icu3/9 ** (fetching) 55 37 icr39 320 h 000fff20 h 39 icu4/10 ** (fetching) 56 38 icr40 31c h 000fff1c h 40 icu5/11 ** (fetching) 57 39 icr41 318 h 000fff18 h 41 ocu0/1(match) 58 3a icr42 314 h 000fff14 h 42 ocu2/3(match) 59 3b icr43 310 h 000fff10 h 43 base timer 0 irq0 / base timer 0 irq1 / sound generator 2/ multi - function serial interface ch.11 ( reception completed ) ** / multi - function serial interface ch.11(status) ** 60 3c icr44 30c h 000fff0c h 44 base timer 1 irq0 / base timer 1 irq1/ sound generator3 / xbs ram single bit error generation / ahb ram single bit error generation ** / backup ram single bit error generation/ multi - function serial interface ch.11 ( transmission completed ) ** 61 3d icr45 308 h 000fff08 h 45* 4 dmac0/1/2/3/4/5/6/7/8/ 9/10/11/12/13/14/15 62 3e icr46 304 h 000fff04 h - delay interrupt 63 3f icr47 300 h 000fff00 h - system reserved (used for realos tm * 5 .) 64 40 - 2fc h 000ffefc h - system reserved (used for realos.) 65 41 - 2f8 h 000ffef8 h - used with the int instruction. 66 | 255 42 | ff - 2f4 h | 000 h 000ffef4 h | 000ffc00 h - document number: 002- 04727 rev. *b page 108 of 174 mb91590 series *1 : does not support a dma transfer request caused by an interrupt generated from a peripheral to which no rn (resource number) is assigned. *2 : the status of the multi - function serial interface does not support a dma transfer caused by i 2 c reception. *3 : the clock calibration unit does not support a dma transfer caused by an interrupt. *4 : ram ecc bit error does not support a dma transfer caused by an interrupt. *5 : realos is a trademark of cypre ss *6 : an interrupt of up/down counter ch.2 does not support a dma transfer. *7 : an interrupt related gdc does not support a dma transfer. ** : only supported by mb91f59a/b udcn: up/down counter ch.n icun: input capture unit.n ocun: output compare unit.n document number: 002- 04727 rev. *b page 109 of 174 mb91590 series 11. electrical characteristics 11.1 absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage *1,*2 v cc 5 vss - 0.3 vss+6.0 v v cc 3 vss - 0.3 vss+4.0 v vcc3 vcc5 dvcc vcc5 avrh5 avcc5 vcc5 avr3 avcc3 vcc3 avrh5 avcc5 avr3 avcc3 |i i i i i i i document number: 002- 04727 rev. *b page 110 of 174 mb91590 series *7 : output of p60 - p87 pins. *8 : output of 3v pin. *9 : corresponding pins: all general - purpose ports except p90/adtg.(except for the dedicated analog port) ? use within recommended operating conditions. ? use at dc voltage (current). ? the + b signal should always be applied by connecting a limiting resistor between the + b signal and the microcontroller. ? the value of the limiting resistor should be set so that the current input to the m icrocontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the + b signal is input. ? note that when the microcontroller drive current is low, such as in the low power consumption modes, the + b input potenti al can increase the potential at the vcc pin via a protective diode, possibly affecting other devices. ? note that if the + b signal is input when the microcontroller is off (not fixed at 0 v), since the power is supplied through the pin, the microcontroller may operate incompletely. ? note that if the +b signal is input at power - on, since the power is supplied through the pin, the power - on reset may not function in the power supply voltage. ? do not leave + b input pins open. sample recommended circuit mb91590 series + b input (12 to 16v) protective diode limiting resistor current *10 : to use this product at t a =105c, equip this on a multilayer board with four or more layers. warning semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. do not exceed any of these ratings. document number: 002- 04727 rev. *b page 111 of 174 mb91590 series 11.2 recommended operating conditions (v ss =dv ss =av ss =0.0v) parameter symbol value unit remarks min max power supply voltage v cc 5 4.5 5.5 v recommended operation guarantee range dv cc 4.5 5.5 v av cc 5 4.5 5.5 v v cc 3 3.0 3.6 v av cc 3 3.0 3.6 v v cc 5 3.5 5.5 v operation guarantee range dv cc 3.5 5.5 v av cc 5 3.5 5.5 v v cc 3 2.7 3.6 v av cc 3 2.7 3.6 v smoothing capacitor * c s 4.7 (tolerance within 50%) f use a ceramic capacitor or a capacitor that has the similar frequency characteristics. use a capacitor with a capacitance greater than c s as the smoothing capacitor on the vcc pin. operating temperature t a - 40 +105 c *: see the following diagram for details on the connection of smoothing capacitor c s . ? c pin connection diagram c s c_1 v ss av ss dv ss c_2 c_3 c s warning the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. any use of semiconducto r devices will be under their recommended operating condition. operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. no warranty is made with resp ect to any use, operating conditions or combinations not represented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. document number: 002- 04727 rev. *b page 112 of 174 mb91590 series 11.3 dc characteristics (t a : recommended operating conditions, v c c 5=5.0v 10%, v cc 3=3.3v 10%, v ss =dv ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max "h" level input voltage v ih1 p060 to p067, p070 to p077, p080 to p087, p090 to p097, p100 to p107, p110 to p117, p120 to p127, p130 to p137 cmos input level is selected 0.7 v cc 5 ? v cc 5+ 0.3 v v ih2 cmos hysteresis input level is selected 0.7 v cc 5 ? v cc 5+ 0.3 v v ih3 automotive input level is selected 0.8 v cc 5 ? v cc 5+ 0.3 v v ih4 ttl input level is selected 2.0 ? v cc 5+ 0.3 v v ih5 rstx, nmix, md2 ? 0.7 v cc 5 ? v cc 5+ 0.3 v v ih7 md0,md1 ? 0.7 v cc 5 ? v cc 5+ 0.3 v v ih8 debugif ? 2.0 ? v cc 5+ 0.3 v v ih10 p000 to p007, p010 to p017, p020 to p027, p030 to p037, p040 to p047, p050 to p057, pa2 to pa7, pb2 to pb7, pc2 to pc7, pd2 to pd7, pe2 to pe7, pf2 to pf7, pg0 to pg7, ph3 cmos hysteresis input level is selected 0.7 v cc 3 ? v cc 3+ 0.3 v 3.3v dedicated pin v ih11 ttl input level is selected 2.0 ? v cc 3+ 0.3 v v ih12 md3 - 0.8 v cc 5 - v cc 5+ 0.3 v bga product only v ih13 tdi, tms, trst, tck - 0.7 v cc 5 - v cc 5+ 0.3 v bga product only document number: 002- 04727 rev. *b page 113 of 174 mb91590 series (t a : recommended operating conditions, v cc 5=5.0v 10%, v cc 3=3.3v 10%, v ss =dv ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max "h" level output voltage v oh1 p060 to p067, p070 to p077, p080 to p087, p090 to p097, p100 to p107, p110 to p117, p120 to p127, p130 to p137 v cc 5 = 4.5v i oh = - 1.0ma v cc 5 - 0.5 ? v cc 5 v v oh2 v cc 5 = 4.5v i oh = - 2.0ma v cc 5 - 0.5 ? v cc 5 v v oh3 p060 to p067, p070 to p077, p080 to p087 dv cc = 4.5v i oh = - 30.0ma dv cc - 0.5 ? dv cc v smc shared pin v oh4 p000 to p007, p010 to p017, p020 to p027, p030 to p037, p040 to p047, p050 to p057, pa2 to pa7, pb2 to pb7, pc2 to pc7, pd2 to pd7, pe2 to pe7, pf2 to pf7, pg0 to pg7, ph3 v cc 3 = 3.0v i oh = - 2.0ma v cc 3 - 0.5 ? v cc 3 v 3.3v dedicated pin v oh5 v cc 3 = 3.0v i oh = - 5.0ma v oh6 v cc 3 = 3.0v i oh = - 10.0ma v oh7 v cc 3 = 3.0v i oh = - 20.0ma v oh8 tdo v cc 5 = 4.5v i oh = - 5.0ma v cc 5 - 0.5 ? v cc 5 v bga product only document number: 002- 04727 rev. *b page 114 of 174 mb91590 series (t a : recommended operating conditions, v cc 5=5.0v 10%, v cc 3=3.3v 10%, v ss =dv ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max "l" level input voltage v il1 p060 to p067, p070 to p077, p080 to p087, p090 to p097, p100 to p107, p110 to p117, p120 to p127, p130 to p137 cmos input level is selected vss- 0.3 ? 0.3 v cc 5 v v il2 cmos hysteresis input level is selected vss- 0.3 ? 0.3 v cc 5 v v il3 automotive input level is selected vss- 0.3 ? 0.5 v cc 5 v v il4 ttl input level is selected vss- 0.3 ? 0.8 v v il5 rstx, nmix, md2 ? vss- 0.3 ? 0.3 v cc 5 v v il7 md0, md1 ? vss- 0.3 ? 0.3 v cc 5 v v il8 debugif ? vss - 0.3 ? 0.8 v v il10 p000 to p007, p010 to p017, p020 to p027, p030 to p037, p040 to p047, p050 to p057, pa2 to pa7, pb2 to pb7, pc2 to pc7, pd2 to pd7, pe2 to pe7, pf2 to pf7, pg0 to pg7, ph3 cmos hysteresis input level is selected vss- 0.3 ? 0.3 v cc 3 v 3.3v dedicated pin v il11 ttl input level is selected vss- 0.3 ? 0.8 v v il12 md3 - v ss - 0.3 - 0.3 v cc5 v bga product only v il13 tdi, tms, trst, tck - v ss - 0.3 - 0.3 v cc5 v bga product only document number: 002- 04727 rev. *b page 115 of 174 mb91590 series (t a : recommended operating conditions, v cc 5=5.0v 10%, v cc 3=3.3v 10%, v ss =dv ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max "l" level output voltage v ol1 p060 to p067, p070 to p077, p080 to p087, p090 to p097, p100 to p107, p110 to p117, p120 to p127, p130 to p137 v cc 5 = 4.5v i ol = 1.0ma 0 ? 0.4 v v ol2 v cc 5 = 4.5v i ol = 2.0ma 0 ? 0.4 v v ol3 p060 to p067, p070 to p077, p080 to p087 dv cc = 4.5v i ol = 30.0ma 0 ? 0.55 v smc shared pin v ol4 p127, p130, p132, p133 v cc 5 = 4.5v i ol = 3.0ma 0 ? 0.4 v i 2 c shared pin (i 2 c is selected) v ol5 debugif v cc 5 = 2.7v i ol = 25.0ma 0 ? 0.25 v v ol6 p000 to p007, p010 to p017, p020 to p027, p030 to p037, p040 to p047, p050 to p057, pa2 to pa7, pb2 to pb7, pc2 to pc7, pd2 to pd7, pe2 to pe7, pf2 to pf7, pg0 to pg7, ph3 v cc 3 = 3.0v i ol = 2.0ma 0 ? 0.4 v 3.3v dedicated pin v ol7 v cc 3 = 3.0v i ol = 5.0ma v ol8 v cc 3 = 3.0v i ol = 10.0ma v ol9 v cc 3 = 3.0v i ol = 20.0ma v ol10 tdo v cc 5 = 4.5v i oh = 5.0ma 0 ? 0.4 v bga product only document number: 002- 04727 rev. *b page 116 of 174 mb91590 series (t a : recommended operating conditions, v cc 5=5.0v 10%, v cc 3=3.3v 10%, v ss =dv ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max input leak current ii l all input pins vcc=dvcc= avcc=5.5v vss document number: 002- 04727 rev. *b page 118 of 174 mb91590 series parameter symbol pin name conditions value unit remarks min typ max high current output drive capacity phase -to - phase deviation1 v oh3 pwm1pn, pwm1mn, pwm2pn, pwm2mn, n=0 to 5 dvcc=4.5v i oh = - 30.0ma maximum deviation of v oh3 ? ? 90 mv *2 high current output drive capacity phase -to - phase deviation2 v ol3 pwm1pn, pwm1mn, pwm2pn, pwm2mn, n=0 to 5 dvcc=4.5v i ol =30.0ma maximum deviation of v ol3 ? ? 90 mv *2 *1 : the power supply current value when the external clock is supplied from the x1 pin. note that the power supply current value when using the external clock is different from that using the oscillator. *2 : if pwm1p0/pwm1m0/pwm2p0/pwm2m0 of ch.0 is turned on simultaneously, the maximum deviation of v oh3 / v ol3 for each pin is defined. same for other channels. *3 : this product contains both program flash and wo rkflash. this parameter is defined when only one of them is in the write/erase state. *4 : mb91f591/2/4/6/7/9 *5 : mb91f59a/b document number: 002- 04727 rev. *b page 119 of 174 mb91590 series 11.4 ac characteristics 11.4.1 main clock timing (t a : recommended operating conditions, v cc 5=5.0v 10%, v ss =dv ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max source oscillation clock frequency f c x0, x1 ? ? 4 ? mhz source oscillation clock cycle time t cyl x0, x1 ? 250 ? ns internal operating clock frequency* 1 , * 2 f cp ? ? 2 ? 128 mhz cpu clock f cpp ? ? 2 ? 40 mhz peripheral bus clock internal operating clock cycle time* 1 , * 2 t cp ? ? 7.8125 ? 500 ns cpu clock t cpp ? ? 25 ? 500 ns peripheral bus clock can pll jitter (when lock) t pj ? ? -10 ? +10 ns built - in cr oscillation frequency f ccr ? ? 50 100 200 khz *1 : the maximum frequency of cpu clock is described in the table of product type. *2 : the maximum / minimum value is defined when using the main clock and pll clock. ? x0,x1 clock timing x0 cyl ? can pll jitter deviation time from the ideal clock is assured per cycle out of 20, 000 cycles. t1 t2 t3 t1 pl l output ideal clock deviation time slow fast t2 t3 tn-1 tn tn-1 tn document number: 002- 04727 rev. *b page 120 of 174 mb91590 series 11.4.1.1 sub clock timing (products without s - suffix) (t a : recommended operating conditions, v cc 5=5.0v 10%, v ss =dv ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max source oscillation clock frequency f cl x0a, x1a ? ? 32.768 ? khz source oscillation clock cycle time t lcyl x0a, x1a ? ? 30.52 ? s ? x0a,x1a clock timing x0a lcyl document number: 002- 04727 rev. *b page 121 of 174 mb91590 series guaranteed operation range (5v operating microcontroller section ) internal operation clock frequency vs. power supply voltage internal operation clock frequency f cp (mhz) 128 4 2 3. 5 5.5 power supply voltage v cc 5 (v) g uaranteed operation range pll guaranteed operation range 4.5 r ecommended guaranteed operation range note: the cpu will be reset at the power supply voltage 4v0.3v or less. oscillation clock frequency vs. internal operation clock frequency internal operation clock frequency main clock pll clock multiplie d by 1 multiplie d by 2 multiplie d by 3 multiplie d by 4 ... multiplie d by 20 multiplie d by 32 oscillation clock frequency 4mhz 2mhz 4mhz 8mhz 12mhz 16mhz ... 80mhz 128mhz ? example of oscillation circuit note: as to the product with its clock supervisor?s initial value is "on", when the oscillator is unable to start within 20ms from the stop state the clock supervisor will detect the oscillation stop. as a result, the cpu moves to the fail safe operation. design your printed circuit board so that the oscillator can start oscillation within 20ms. x1 x0 r = 0 document number: 002- 04727 rev. *b page 122 of 174 mb91590 series ac characteristics are specified by the following measurement reference voltage values. ? input signal waveform ? output signal waveform hysteresis input pin (automotive) 0.5vcc 5 0.8vcc 5 output pin 0.8v 2.4v hysteresis input pin (cmos normal) 0. 3 vcc 5 0. 7 vcc 5 hysteresis input pin (cmos hysteresis) 0.3vcc 5 0.7vcc 5 ttl input pin 0.8v 2.0v document number: 002- 04727 rev. *b page 123 of 174 mb91590 series 11.4.1.2 reset input (t a : recommended operating conditions, v cc 5=5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min max reset input time t rstl rstx ? 10 ? s when normal operation oscillation time of oscillator* + 100s 100s 1s ? s *: the oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%. for crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is between several hundred s and several ms, and for an external clock, the time is 0 ms. rstx 0.2vcc 5 0.2vcc 5 t rstl ? at stop mode 0.2 v cc 5 100 s rstx x0 90% of amplitude oscillation time of oscillator oscillation stabilization waiting time instruction execution internal reset 0.2 v cc 5 t rstl document number: 002- 04727 rev. *b page 124 of 174 mb91590 series 11.4.1.3 power - on conditions (t a : recommended operating conditions, v ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max level detection voltage ? v cc 5 ? 2.1 2.3 2.5 v when turning on power for microcontroller level detection hysteresis width ? v cc 5 ? ? ? 125 mv during voltage drop level detection time ? ? ? ? ? 30 us *1 specification for voltage slope detection ? v cc 5 v cc 5 = at level detection release level time ? ? 4 mv/s *2 power off time t off v cc 5 ? 50 ? ? ms *3 *1 : if the fluctuation of the power supply is faster than the low voltage detection time, there is the possibility to generate or re lease after the power supply voltage has exceeded the detection voltage range. *2 : when setting the power supply fluctuation to this specification or less, it is possible to suppress the voltage slope detection. t his is the specification when the power supply fluctuation is stable. *3 : this t ime is to start the voltage slope detection at next power on after power down and internal charge loss. document number: 002- 04727 rev. *b page 125 of 174 mb91590 series 11.4.1.4 multi - function serial uart timing ? bit setting: smr: md2=0, smr: md1=1, smr: md0=0, smr: scinv=0, scr: spi=0 (t a : recommended operating conditions, v cc 5=5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sckx ? 4t cpp ? ns internal shift clock mode: c l =50pf (when drive capability is 2ma or more.) c l =20pf (when drive capability is 1ma) sck valid sin sck setup time sck sck valid sin sck setup time sck document number: 002- 04727 rev. *b page 126 of 174 mb91590 series ? i n t e r na l s h i ft c l o c k m o d e 2 . 4 v 2 . 4 v 0 . 8 v 0 . 8 v s i n x s o t x s c k x t s c y c t s l o v i t s h i x i t i vs h i 0 . 8 v v i h v i l v i h v i l ? e x t e r na l s h i f t c l o c k m o d e 2 . 4 v v i h 0 . 8 v s i n x s o t x s c k x t s l s h t s l o v e t s h i x e t i vs h e t s h s l v i l t f t r v i h v i l v i h v i l v i h v i l v i l v i h document number: 002- 04727 rev. *b page 127 of 174 mb91590 series ? bit setting: smr: md2=0, smr: md1=1, smr: md0=0, smr: s cinv=1, scr: spi=0 (t a : recommended operating conditions, v cc 5=5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sckx ? 4t cpp ? ns internal shift clock mode: c l =50pf (when drive capability is 2ma or more.) c l =20pf (when drive capability is 1ma) sck valid sin sck setup time sck sck valid sin sck setup time sck notes : ? ac characteristic in clk synchronized mode. ? c l is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by internal operation clock used and other parameters. ? see hardware manual for details. ? "x" means channel number of 0, 1, 8, 9, 10, and 11 for sckx, sinx and sotx. document number: 002- 04727 rev. *b page 128 of 174 mb91590 series ? internal shift clock mode t shovi 2.4v 2.4v 0.8v 0.8v sinx sotx sckx t slixi t ivsli v ih v il v ih v il 2.4v t scyc ? external shift clock mode t shsl v v il v ih v il v il v ih 2.4v v ih 0.8v sinx sotx sckx t shove t slixe t ivsle v ih v il t r t f v ih t slsh v il document number: 002- 04727 rev. *b page 129 of 174 mb91590 series ? bit setting: smr: md2=0, smr: md1=1, smr: md0=0, smr: scinv=0, scr: spi=1 (t a : recommended operating conditions, v cc 5=5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit min max serial clock cycle time t scyc sckx internal shift clock mode c l =50pf (when drive capability is 2ma or more.) c l =20pf (when drive capability is 1ma) 4t cpp ? ns sck sot delay valid sin sck sck sot sck sck valid sin sck sck notes: ? ac characteristic in clk synchronized mode. ? c l is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by internal operation clock used and other parameters. ? see hardware manual for details. ? "x" means channel number of 0, 1, 8, 9, 10, and 11 for sckx, sinx and sotx. document number: 002- 04727 rev. *b page 130 of 174 mb91590 series ? internal shift clock mode ? external shift clock mode *: changes when writing to tdr register t scyc t shovi t sovli t slixi t ivsli 2.4v 2.4v 0.8v 0.8v v ih v il v ih v il 2.4v 0.8v 0.8v sckx sotx sinx t slsh t shsl t shove t r t f t slixe t ivsle 2.4v 0.8v v ih v il v il v il v il v ih v ih v ih v ih v il 2.4v 0.8v sckx * sotx sinx document number: 002- 04727 rev. *b page 131 of 174 mb91590 series ? bit setting: smr: md2=0, smr: md1=1, smr: md0=0, smr: scinv=1, scr: spi=1 (t a : recommended operating conditions, v cc 5=5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit min max serial clock cycle time t scyc sckx internal shift clock mode c l =50pf(when drive capability is 2ma or more.) c l =20pf(when drive capability is 1ma) 4t cpp ? ns sck sot delay valid sin sck sck sot sck delay sck sot delay valid sin sck sck notes : ? ac characteristic in clk synchronized mode. ? c l is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by internal operation clock used and other parameters. ? see hardware manual for details. ? "x" means channel number of 0, 1, 8, 9, 10, and 11 for sckx, sinx and sotx. document number: 002- 04727 rev. *b page 132 of 174 mb91590 series ? internal shift clock mode ? external shift clock mode *: changes when writing to tdr register t scyc t slovi t sovhi t shixi t ivshi 2.4v 2.4v 2.4v 0.8v 0.8v v ih v il v ih v il 2.4v 0.8v sckx sotx sinx t slsh t shsl t slove t r t f t shixe t ivshe 2.4v 0.8v v ih v il v il v il v il v ih v ih v ih v ih v il 2.4v 0.8v sckx * sotx sinx document number: 002- 04727 rev. *b page 133 of 174 mb91590 series external clock (ext = 1): asynchronous only (t a : recommended operating conditions, v cc 5=5.0v10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit min max serial clock "h" pulse width t shsl sckx c l =50pf (when drive capability is 2ma or more.) c l =20pf (when drive capability is 1ma) t cpp +10 - ns serial clock "l" pulse width t slsh t cpp +10 - ns sck fall time t f - 5 ns sck rise time t r - 5 ns note: "x" means channel number of 0, 1, 8, 9, 10, and 11 for sckx, sinx and sotx. t shs l v il v il v il v ih v ih v ih t r t f t slsh s ck document number: 002- 04727 rev. *b page 134 of 174 mb91590 series i 2 c timing (t a : recommended operating conditions, v cc 5=5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions standard mode high - speed mode unit remarks min max min max scl clock frequency f scl sck0, sck1 c l =50pf (when drive capability is 2ma or more.) c l =20pf (when drive capability is 1ma) r = (v p /i ol ) *1 0 100 0 400 khz repeat "start" condition hold time sda scl t hdsta sot0, sot1, (sda) sck0, sck1, (scl) 4.0 ? 0.6 ? s period of "l" for scl clock t low sck0, sck1, (scl) 4.7 ? 1.3 ? s period of "h" for scl clock t high sck0, sck1, (scl) 4.0 ? 0.6 ? s repeat "start" condition setup time scl sda s data hold time scl sda t hddat sot0, sot1, (sda) sck0, sck1, (scl) 0 3.45 *2 0 0.9 s data setup time sda scl t sudat sot0, sot1, (sda) sck0, sck1, (scl) 250 *3 ? 100 ? ns "stop" condition setup time scl sda s bus - free time between "stop" condition and "start" condition t buf ? 4.7 ? 1.3 ? s noise filter t sp ? ? 2t cpp *4 ? 2t cpp *4 ? ns *1 : r and c l represent the pull - up resistance and load capacitance of the scl and sda output lines, respectively. vp shows that the power - supply voltage of the pull - up resistor and i ol shows the v ol guarantee current. *2 : the maximum t hddat only has to be met if the device does not extend the "l" width (t low ) of the scl signal. *3 : a high - speed mode i 2 c bus device can be used on a standard mode i 2 c bus system as long as the device satisfies the re quirement of "t sudat 250 ns". *4 : t cpp is the peripheral clock cycle time. adjust the peripheral clock frequency to 8mhz or more when use i 2 c. document number: 002- 04727 rev. *b page 135 of 174 mb91590 series sda scl t hdsta t low t hddat t sudat t high t susta t hdsta t sp t buf t susto document number: 002- 04727 rev. *b page 136 of 174 mb91590 series 11.4.1.5 lin - uart timing ? bit setting: escr: sces=0, eccr: scde=0 (t a : recommended operating conditions, v cc 5=5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sck2,sck3, sck4,sck5, sck6,sck7 ? 5t cpp ? ns internal shift clock mode: c l =80pf + 1 ? ttl sck sot delay time t slovi sck2,sck3, sck4,sck5, sck6,sck7, sot2,sot3, sot4,sot5, sot6,sot7 -50 +50 ns valid sin sck setup time sck valid sin hold time t shixi 0 ? ns serial clock "l" pulse width t slsh sck2,sck3, sck4,sck5, sck6,sck7 ? 3t cpp -t r ? ns external shift clock mode: c l =80pf + 1 ? ttl serial clock "h" pulse width t shsl t cpp +10 ? ns sck sot delay time t slove sck2,sck3, sck4,sck5, sck6,sck7, sot2,sot3, sot4,sot5, sot6,sot7 ? 2t cpp +60 ns valid sin sck setup time sck valid sin hold time t shixe t cpp +30 ? ns sck fall time t f sck2,sck3, sck4,sck5, sck6,sck7 ? 10 ns sck rise time t r ? 40 ns notes : ? c l is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by internal operation clock used and other parameters. ? see hardware manual for details. document number: 002- 04727 rev. *b page 137 of 174 mb91590 series ? internal shift clock mode 2.4v 2.4v 0.8v 0.8v sin x sot x sck x t scyc t slovi ? external shift clock mode 2 . 4 v 0 . 8 v s i n x s o t x s c k x t s l s h t s l o v e t s h i x e t i vs h e v i h v i l t s h s l t f t r v i h v i l v i l v i h v i h v i l v i h v i l document number: 002- 04727 rev. *b page 138 of 174 mb91590 series ? bit setting: escr: sces=1, eccr: scde=0 (t a : recommended operating conditions, v cc 5=5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sck2,sck3, sck4,sck5, sck6,sck7 ? 5t cpp ? ns internal shift clock mode: c l =80pf+1 ? ttl sck sot delay time t shovi sck2,sck3, sck4,sck5, sck6,sck7, sot2,sot3, sot4,sot5, sot6,sot7 -50 +50 ns valid sin sck setup time sck valid sin hold time t slixi 0 ? ns serial clock "h" pulse width t shsl sck2,sck3, sck4,sck5, sck6,sck7 ? 3t cpp -t r ? ns external shift clock mode: c l =80pf+1 ? ttl serial clock "l" pulse width t slsh t cpp +10 ? ns sck sot delay time t shove sck2,sck3, sck4,sck5, sck6,sck7, sot2,sot3, sot4,sot5, sot6,sot7 ? 2t cpp +60 ns valid sin sck setup time sck valid sin hold time t slixe t cpp +30 ? ns sck fall time t f sck2,sck3, sck4,sck5, sck6,sck7 ? 10 ns sck rise time t r ? 40 ns notes : ? c l is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by internal operation clock used and other parameters. ? see hardware manual for details. document number: 002- 04727 rev. *b page 139 of 174 mb91590 series ? internal shift clock mode 2.4v 2.4v 0.8v 0.8v sin x sot x sck x t scyc t shovi ? external shift clock mode 2 . 4 v 0 . 8 v s i n x s o t x s c k x t s h s l t s h o v e t s l i x e t i v s l e v i h v i l t s l s h t r t f v i h v i l v i h v i l v i h v i l v i l v i h document number: 002- 04727 rev. *b page 140 of 174 mb91590 series ? bit setting: escr: sces=0, eccr: scde=1 (t a : recommended operating conditions, v cc 5=5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sck2,sck3, sck4,sck5, sck6,sck7 ? 5t cpp ? ns internal shift clock mode: c l =80pf + 1 ? ttl sck sot delay time t shovi sck2,sck3, sck4,sck5, sck6,sck7, sot2,sot3, sot4,sot5, sot6,sot7 -50 +50 ns valid sin sck setup time sck valid sin hold time t slixi 0 ? ns sot sck delay time t sovli sck2,sck3, sck4,sck5, sck6,sck7, sot2,sot3, sot4,sot5, sot6,sot7 3t cpp -70 ? ns notes : ? c l is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by internal operation clock used and other parameters. ? see hardware manual for details. ? internal shift clock mode 2.4v 2.4v 0.8v 0.8v sin x sot x sckx t scyc t slixi t ivsli v ih v il v il v ih 0.8v 2.4v 0.8v t shovi t sovli document number: 002- 04727 rev. *b page 141 of 174 mb91590 series ? bit setting: escr: sces=1, eccr: scde=1 (t a : recommended operating conditions, v cc 5=5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sck2,sck3, sck4,sck5, sck6,sck7 ? 5t cpp ? ns internal shift clock mode: c l =80pf+1 ? ttl sck sot delay time t slovi sck2,sck3, sck4,sck5, sck6,sck7, sot2,sot3, sot4,sot5, sot6,sot7 -50 +50 ns valid sin sck setup time sck valid sin hold time t shixi 0 ? ns sot sck delay time t sovhi sck2,sck3, sck4,sck5, sck6,sck7, sot2,sot3, sot4,sot5, sot6,sot7 3t cpp -70 ? ns notes : ? c l is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by internal operation clock used and other parameters. ? see hardware manual for details. ? internal shift clock mode 2.4v 2.4v 0.8v 0.8v sin x sot x sck x t scyc t shixi document number: 002- 04727 rev. *b page 142 of 174 mb91590 series 11.4.1.6 timer input timing (t a : recommended operating conditions, v cc 5=5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh , t tiwl tin0 to tin3, tin7 to tin10, icu0 to icu11, frck0 to frck7, tioa,tiob, udcain0 to 2, udcbin0 to 2, udczin0 to 2 ? 4t cpp ? ns ? timer input timing v ih v il t tiwl t tiwh v il tinx , icux , frck0, frck1 , tioa, tiob v ih note : the description can be applied to frck2 to 7, udcain0 to 2, udcbin0 to 2, and udczin0 to 2 as well. 11.4.1.7 trigger input timing (t a : recommended operating conditions, v cc 5=5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh , t trgl int0 to int15, adtg, rx0, rx1, rx2 ? 5t cpp ? ns 1 ? s at stop mode ? trigger input timing v ih v il adtg , t trgl t trgh v il intx , rxx v ih document number: 002- 04727 rev. *b page 143 of 174 mb91590 series 11.4.1.8 nmi input timing (t a : recommended operating conditions, v cc 5=5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min max input pulse width t nmil nmix ? 4t cpp ? ns ? nmix input timing v ih nmix t nmil v ih document number: 002- 04727 rev. *b page 144 of 174 mb91590 series 11.4.1.9 low voltage detection (external low - voltage detection) (t a : recommended operating conditions, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max power supply voltage range v cc5 vcc5 ? ? ? 5.5 v microcontroller unit v cc 3 vcc3 ? ? ? 3.6 v gdc unit detection voltage v dl vcc5 *1 3.9 4.1 4.3 v when power - supply voltage falls at microcontroller unit and detection level is set initially vcc3 *1 2.2 2.4 2.6 v when power - supply voltage falls at gdc unit and detection level is set initially hysteresis width v hys vcc5/ vcc3 ? ? ? 125 mv when power - supply voltage rises low voltage detection time td ? ? ? ? 30 s power supply voltage fluctuation rate ? vcc5, vcc3 ? -2 ? 2 v/ms *2 *1: if the fluctuation of the power supply is faster than the low voltage detection time(td), there is a possibility to generate or release after the power supply voltage has exceeded the detection voltage range. *2: in order to perform the low - voltag e detection at the detection voltage (v dl ), be sure to suppress fluctuation of the power supply voltage within the limits of the power supply voltage fluctuation rate. document number: 002- 04727 rev. *b page 145 of 174 mb91590 series 11.4.1.10 low voltage detection (internal low - voltage detection) (t a : recommended operating conditions, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max power supply voltage range v rdp5 vcc ? ? ? 1.3 v detection voltage v rdl * 0.8 0.9 1.0 v when power - supply voltage falls hysteresis width v rhys ? ? ? 50 mv when power - supply voltage rises low voltage detection time td ? ? ? ? 30 s *: if the fluctuation of the power supply is faster than the low voltage detection time(td), there is a possibility to generate or release after the power supply voltage has exceeded the detection voltage range. document number: 002- 04727 rev. *b page 146 of 174 mb91590 series 11.4.1.11 high current output slew rate (t a : recommended operating conditions, v cc 5=av cc 5=5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max output rise /fall time t r2 , t f2 p060 to p067, p070 to p077, p080 to p087 ? 15 ? 100 ns load capacitance 85pf ? slew rate output timing v h =v ol2 +0.9 (v oh2 -v ol2 ) v l =v ol2 +0.1 (v oh2 -v ol2 ) + + t f2 t r2 v l v l v h v h document number: 002- 04727 rev. *b page 147 of 174 mb91590 series 11.4.1.12 external memory interface memory controller (t a : recommended operating conditions, v cc 3=3.3v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min max chip select delay time t cso mem_xcs0, mem_xcs1 12pf/10ma ? 18 ns *1 ? 14 ns *2 address delay time t ao mem_ea[24:0] ? 18 ns *1 ? 14 ns *2 data output delay time t do mem_ed[15:0] ? 18 ns *1 ? 17 ns *2 data output hiz time t doz ? 18 ns *1 ? 17 ns *2 nor flash data setup time t dsr 20 ? ns *1 11 ? ns *2 nor flash data hold time t dhr 0 ? ns *1 0 ? ns *2 nor flash page read data setup time t dsp 20 ? ns *1 8.5 ? ns *2 nor flash page read data hold time t dhp 0 ? ns *1 0 ? ns *2 xrd delay time t rdo mem_xrd ? 18 ns *1 ? 14 ns *2 xwr delay time t wro mem_xwr ? 18 ns *1 ? 14 ns *2 output delay is reference clock is an internal clock. the reference clock of mem_rdy is an internal clock. *1: mb91f591/2/4/6/7/9 *2: mb91f59a/b document number: 002- 04727 rev. *b page 148 of 174 mb91590 series ? nor flash read timing internal clk mem_xcs0 mem_xcs1 mem_ea[24:0] mem_xrd mem_ed[15:0] t cso t ao t dsr t dhr mem_rdy t rdo t rdo t cso t ao document number: 002- 04727 rev. *b page 149 of 174 mb91590 series ? nor flash write timing ? nor flash page read timing internal clk mem_xcs0 mem_xcs1 mem_ea[24:0] mem_xwr mem_ed[15:0] t cso t ao mem_rdy t wro t wro t do t do x t cso t ao t do i n t e r n a l cl k mem_xcs0 mem_xcs1 mem_ea[24:0] mem_xrd mem_ed[15:0] t c s o t a o t d s p t d hp mem_rdy t c s o t a o t r d o t a o t d s p t d hp document number: 002- 04727 rev. *b page 150 of 174 mb91590 series hs -spi (t a : recommended operating conditions, v cc 3=3.3v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scycm spi_clk c l =12pf (when drive capability is 10ma) 25 ? ns rtm=1, mode=0,1,3 50 other than those above valid cs clk valid cs clk clk end invalid clk end invalid document number: 002- 04727 rev. *b page 151 of 174 mb91590 series t scycm t oslsk02 t osksl02 t oslsk13 t osksl13 spi_clk spi_cs0, spi_cs1, spi_cs2, spi_cs3 mode0 mode2 mode1 mode3 input output t dsset t sdhold t osdat spi_sio0, spi_sio1, spi_sio2, spi_sio3 document number: 002- 04727 rev. *b page 152 of 174 mb91590 series 11.4.1.13 gdc display signal clock ac timing of video interface clock signal (t a : recommended operating conditions, v cc 3=3.3v 10%, v ss =av ss =0.0v) parameter symbol pin name value unit remarks min max dclki frequency fdclki0 dclki ? 54 mhz dclki "h"width thdclki0 18 ? ns dclki "l"width tldclki0 18 ? ns dclk frequency tldclk0 dclk (internal) ? 54 mhz *1 dclko frequency fdclko0 dclko ? 54 mhz *2 *1: the internal display clock of pll synchronous mode is generated with internal pll of display clock prescaler. *2: dclki or pll internal display clock is output. apply only dclki synchronous mode. (reference clock= dclki) ? ac timing of video interface input signal (t a : recommended operating conditions, v cc 3=3.3v 10%, v ss =av ss =0.0v) parameter symbol pin name value unit remarks min typ max hsync input setup time tshsync0 hsync(i) 4 ? ? ns hsync input hold time thhsync0 1 ? ? ns vsync input pulse width twvsync0 vsync(i) 1 ? ? hsync ? display input signal timing twvsync n dclk i n hsync n (i) tshsync n thhsync n thdclki n tldclki n 1/fdclki n vsync n (i) tsvsync n thvsync n twhsync n document number: 002- 04727 rev. *b page 153 of 174 mb91590 series ac characteristics of display output signal ? clock mode there are multiple clock modes for display output clocks, as shown in table 1. the ac timing parameters vary depending on mod es. the ac timing parameters are specified for each mode. table 1 . clock mode for display output setting register bit field clock mode name dcm1 dcm3 cks dcked dckd dckinv 0 0 0 0 built - in pll standard mode 0 0 0 1 built - in pll reverse edge mode 0 1 0 0 cannot be used. 0 1 0 1 0 0 other than 0 0 built - in pll delay mode 0 0 other than 0 1 built - in pll reverse edge and delay mode 0 1 other than 0 0 built - in pll both edge and delay mode 0 1 other than 0 1 1 0 0 0 dclki input standard mode 1 0 0 1 dclki input reverse edge mode 1 1 0 0 cannot be used. 1 1 0 1 1 0 other than 0 0 1 0 other than 0 1 1 1 other than 0 0 1 1 other than 0 1 document number: 002- 04727 rev. *b page 154 of 174 mb91590 series ? ac timing parameters this section describes parameters used for ac timing specifications. select whether you use the dclko reverse edge mode, depending on the use/non - use of delay mode. when the delay mode is not used: use the dclko reverse edge mode when the external display device (tft) receives the signal at the rising edge of dclko. use the dclko standard mode when the external display device (tft) receives the signal at the falling edge of dclko. when the delay mode is used: use the dclko standard mode when the external display device (tft) receives the signal at the rising edge of dclko. use the dclko reverse edge mode when the external display device (tft) receives the signal at the falling edge of dclko. note: clock duty ratio when the clock frequency division ratio is even or odd ac specifications use the half - cycle of the display output clock dclko as a paramete r. in ac specifications, the first half - cycle is indicated as t dcyc_f , and the second half - cycle is indicated as t dcyc_l . note that clock duty ratio will not be 50%:50% when the clock frequency division ratio (specified in sc field of dcm1 registe r) is odd . if the clock frequency division ratio is odd, the first half - cycle t dcyc_f becomes different from the second half - cycle t dcyc_l . figure 2 . clock duty ratio when the clock frequency division ratio is even or odd dclko (dckinv=1) t dcyc / 2 t dcyc t dcyc / 2 dclko (dckinv=1) t dcyc / 3 t dcyc 2 (t dcyc / 3) t dcyc_f t dcyc_l t dcyc_f t dcyc_l ? when the frequency division ratio is even ? example: when the frequency division ratio is odd (frequency division ratio = 3) when the clock frequency division ratio is 5, t dcyc_f : t dcyc_l will be 2:3. document number: 002- 04727 rev. *b page 155 of 174 mb91590 series built - in pll reverse edge mode (dcm3.dckinv=1) figure 3 shows the setup/hold definition when the external display device receives the signal at the rising edge of dclko. figure 3 . built - in pll reverse edge mode setup/hold definition built - in pll standard mode (dcm3.dckinv=0) figure 4 shows the setup/hold definition when the external display device receives the signal at the falling edge of dclko. figure 4 . built - in pll standard mode setup/hold definition data signal dclko (dckinv=1) t dosu t dcyc_f t dcyc t dohd use the clock mode of dcm3 register dckinv=1 data signal: rout7~0, gout7~0, bout7~0, hsync, vsync, csout/gv, deout t dcyc_l dc l k o (dck in v = 0 ) data signal t dosu t dcyc t dohd data signal: r o u t 7 ~ 0 , go u t 7 ~ 0 , bo u t 7 ~ 0 , h sy nc , vs y nc , c so u t / g v, d eo u t use the clock mode of dcm3 register dckinv=0 t dcyc_f t dcyc_l document number: 002- 04727 rev. *b page 156 of 174 mb91590 series built - in pll delay mode (dc m3.dckinv=0) figure 5 shows the setup/hold definition when the external display device receives the signal at the rising edge of dclko. (example: when frequency division ratio = 4) figure 5 . built - in pll delay mode setup/hold definition r o u t 7-0 go u t7-0 h sy n c v s y n c d e o u t d c l k o ( dc k i n v= 0 ) ( d e l a y= 3 ) c s o u t/g v bo u t7-0 d c l k o ( dc k i n v= 0) ( d e l a y= 0 ) t p ll c y c t d c y c t d c y c _ f t d c y c _ l t d o s u t d o h d document number: 002- 04727 rev. *b page 157 of 174 mb91590 series built - in pll reverse edge and delay mode (dcm3.dckinv=1) figure 6 shows the setup/hold definition when the external display device receives the signal at the falling edge of dclko. (example: when frequency division ratio = 4) figure 6 . built - in pll reverse edge and delay mode setup/hold definition built - in pll both edge and delay mode (dcm3.dckinv=0) figure 7 shows the setup/hold definition when the external display device (tft) receives the signal both at the rising edge and the falling edge of dclko. (example: when frequency division ratio = 4) although there are two sampling locations in both edg e mode; one at the rising edge and the other at the falling edge, the values of setup/hold definition are same. figure 7 . built - in pll both edge and delay mode setup/hold definition rout7-0 gout7-0 hsync vsync deout csout/gv bout7-0 dclko (dckinv=1) (delay=0) t pllcyc t dcyc t dcyc_f t dcyc_l t dosu t dohd dclko (dckinv=1) (delay=3) rout7-0 gout7-0 hsync vsync deout dclko (delay=3) csout/gv bout7-0 dclko (delay=0) t pllcyc t dcyc t dcyc_f t dcyc_l t dosu t dohd t dosu t dohd document number: 002- 04727 rev. *b page 158 of 174 mb91590 series setup/hold definition in delay mode the delay mode i s a mode realized with dclko delay function, and it can provide delay to dclko signal output itself. this can be used when both the following conditions are satisfied. ? the internal pll is used to generate dclko (cks field of dcm register = 0) ? the frequency division ratio to the internal pll of dclko is 2 or more (sc field of dcm register > 0) the delay value is set as the unit for internal pll clock by dckd field of dcm3 register. the meanings of dckd setting value are shown below. when the internal pll frequency division ratio = 2 when the internal pll frequency division ratio > 2 dckd delay dckd delay 000000 no additional delay 000000 no additional delay 000100 +1 pll clock 000010 +2 pll clock 000100 +3 pll clock 000110 +4 pll clock : : 111110 +17 pll clock in delay mode, t dcyc_f and t dcyc_l are defined by the delay value above (e.g. "2" of "+2 pll clock") as shown below. t dcyc_f = delay value t pllcyc t dcyc_l = t dcyc ? t dcyc_f document number: 002- 04727 rev. *b page 159 of 174 mb91590 series dclki input standard mode (dcm3.dckinv=0) figure 8 shows the setup/hold definition when the external display device (tft) receives the signal at the falling edge of dclko. figure 8 . dclki input standard mode setup/hold definition dclki input reverse edge mode (dcm3.dckinv=1) figure 9 shows the setup/hold definition when the external display device (tft) receives the signal at the rising edge of dclko. figure 9 . dclki input reverse edge mode setup/hold definition data signal d c l k o ( dck i n v = 0 ) t dosu t dcyc_f t dcyc t dohd use the clock mode of dcm3 register dckinv=0 data signal: r o u t 7 ~ 0 , go u t 7 ~ 0 , b o u t 7 ~ 0 , h sync, vsy n c , c s o u t /gv , d e o u t t dcyc_l dclko (dckinv=1) data signal t dosu t dcyc t dohd data signal: rout7~0, gout7~0, bout7~0, hsync, vsync, csout/gv, deout use the clock mode of dcm3 register dckinv=1 t dcyc_f t dcyc_l document number: 002- 04727 rev. *b page 160 of 174 mb91590 series ? ac timing specifications parameter symbol min. display clock cycle time t dcyc 18.5 ns external load condition 50 pf parameter symbol dclko reference edge io drive capability setting remark 10 ma 2 ma setup time t dosu neg, pos *1 t dcyc _f - 8.5ns t dcyc _f - 10.2ns hold time t dohd - t dcyc _l - 1.7ns t dcyc _l - 3.3ns *2 - t dcyc _l - 3.2ns t dcyc _l ? 5.1ns *3 *1: dclko reference edge: this is the reference clock edge for setup time and hold time. pos = the external display device receives the signal at the rising edge of dclko. neg = the external display device receives the signal at the falling edge of dclko. *2: should be applied to rgb666. *3: should be applied to rgb888. document number: 002- 04727 rev. *b page 161 of 174 mb91590 series video capture input parameter symbol pin name value unit remarks min max capture input frequency fci cclk ? 81.0 mhz capture input setup time tcisu bin7 - 2, gin7 -2, rin7 -2, hsin, vsin, vin7 -0 3.0 ? ns capture input hold time tc i h d 0.0 ? ns 1 / f c i t c i s u t c i h d cclk bin7 - 2 gin7 - 2 rin7 - 2 hsin vsin vin7 - 0 document number: 002- 04727 rev. *b page 162 of 174 mb91590 series 11.4.1.14 gdc ommand trigger signal parameter symbol pin name value unit remarks min max input trigger pulse width ttrg cmdtrg 160 ? ns ttrg cmdtrg document number: 002- 04727 rev. *b page 163 of 174 mb91590 series 11.5 a/d converter 11.5.1 electrical characteristics (t a : recommended operating conditions, v cc 5=av cc 5=5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name value unit remarks min typ max resolution ? ? ? ? 10 bit total error ? ? ? ? 3 lsb non linearity error ? ? ? ? 2.5 lsb differential linearity error ? ? ? ? 1.9 lsb zero transition voltage v ot an0 to an31 av ss - 1.5lsb ? av ss + 2.5lsb v 1lsb = (av cc - av ss ) /1024 full - scale transition voltage v fst an0 to an31 avrh5 - 3.5lsb ? avrh5 + 0.5lsb v sampling time t smp ? 1.2 ? ? s s s a v avss v ain v avcc analog input voltage v ain an0 to an31 av ss ? avrh5 v reference voltage a vrh avrh5 4.5 ? 5.5 v avrh5 av a a a note : be sure to use the clock with a frequency between 8mhz and 17mhz for the adc compare clock in order to ensure its accuracy. document number: 002- 04727 rev. *b page 164 of 174 mb91590 series 11.5.2 definition of a/d converter terms resolution : analog variation that is recognized by an a/d converter. non linearity error : deviation of the actual conversion characteristics from a straight line that connects the zero transition point ("00 0000 0000" "00 0000 0001") to the full - v f d o h w u d q v l w l r q s r l q w 8 : differential linearity error : deviation of the input voltage from the ideal value that is required to change the output code by lsb. total error : difference between the actual value and the theoretical value. the total error includes zero transition error, full - scale transition error, and no n linearity error. total error of digital output n = v nt - {1lsb} (n - 1) + 0.5lsb} [lsb] 1lsb 1lsb (ideal value) = avrh5 - avss [v] 1024 n: a/d converter digital output value. v ot (ideal value) = avss + 0.5 lsb[v] v fst (ideal value) = avrh5 - 1.5 lsb[v] v nt : voltage at which the digital output changes from (n - 1) to n. 3ff 3fe 3fd 004 003 002 001 a vss a vrh5 v nt 1.5 lsb 0.5 lsb {1 lsb (n - 1) + 0.5 lsb} actual conversion characteristics (actually-measured value) actual conversion characteristics ideal characteristics digital output analog input t otal error document number: 002- 04727 rev. *b page 165 of 174 mb91590 series linearity error of digital output n = v nt - {1lsb} (n - 1) + v ot [lsb] 1lsb differential linearity error of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst - v ot [v] 1022 v ot : voltage at which the digital output changes from ?000 h ? to ?001 h ?. v fst : voltage at which the digital output changes from ?3fe h ? to ?3ff h ?. 3ff 3fe 3fd 004 003 002 001 avss (avrl) avrh5 avss (avrl) avrh5 n + 1 n n - 1 n - 2 v ot (actual measurement value) {1 lsb (n - 1) + v ot } actual conversion characteristics v fst (actual measurement value) v nt (actual measurement value) actual conversion characteristics ideal characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output digital output analog input non linearity error differential linearity error analog input v nt (actual measurement value) v (n + 1) t (actual measurement value) document number: 002- 04727 rev. *b page 166 of 174 mb91590 series 11.5.3 notes on using a/d converter document number: 002- 04727 rev. *b page 167 of 174 mb91590 series 11.6 flash memory 11.6.1 electrical characteristics parameter value unit remarks min typ max sector erase time ? 200 800 ms 8 kbyte sector *1 , excluding internal preprogramming time ? 300 1100 ms 8 kbyte sector *1 , including internal preprogramming time ? 400 2000 ms 64 kbyte sector *1 , excluding internal preprogramming time ? 700 3700 ms 64 kbyte sector *1 , including internal preprogramming time 8 - bit writing time ? 9 288 s exclusive of overhead time at system level *1 16- bit writing time ? 12 384 s exclusive of overhead time at system level *1 ecc writing time ? 9 288 s exclusive of overhead time at system level *1 erase cycle *2 / data retain time 1,000 cycles/ 20 years, 10,000 cycles/ 10 years, 100,000 cycles/ 5 years ? ? ? average t a =+85c *3 *1 : the guaranteed value for erasure up to 100,000 cycles. *2 : number of erase cycles for each sector. *3 : this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85c). 11.6.2 notes while the flash memory is written or erased, shutdown of the external power (vcc5) is prohibited. in the application system where vcc5 might be shut down while writing or erasing, be sure to turn the power off by using an external voltage detection function. to put it concretely, after the external power supply voltage falls below the detection voltage (v dl * ), hold vcc5 at 2.7v or more within the duration calculated by the following expression: td * [s] + (period of pclk [s] x 257) + 50 [s] *: see " ac characteristics low voltage detection (external low - voltage detection) " document number: 002- 04727 rev. *b page 168 of 174 mb91590 series 12. ordering information part number package *1 mb91f591bpmc - gse1 208- pin plastic lqfp ( lqr208) mb91f591bspmc - gse1 mb91f591bhpmc - gse1 mb91f591bhspmc - gse1 mb91f592bpmc - gse1 mb91f592bspmc - gse1 mb91f592bhpmc - gse1 mb91f592bhspmc - gse1 mb91f594bpmc - gse1 mb91f594bspmc - gse1 mb91f594bhpmc - gse1 mb91f594bhspmc - gse1 mb91f59bceq - gse1 208- pin plastic teqfp ( let208) mb91f59bchseq - gse1 mb91f59acpb - gse1 320- ball grid array package ( bya320) mb91f59acspb - gse1 mb91f59achpb - gse1 mb91f59achspb - gse1 mb91f59bcpb - gse1 mb91f59bcspb - gse1 mb91f59bchpb - gse1 mb91f59bchspb - gse1 *1 : for details of the package , see " package dimensions ". document number: 002- 04727 rev. *b page 169 of 174 mb91590 series 13. package dimensions ? dimension of lqfp -208( lqr208 ) d i m e ns i o n s sy m bo l m in . n o m . m ax . a 1.7 0 a1 0.0 5 0.1 5 b 0 .1 7 0 .2 2 0 .2 7 c 0 .0 9 0 .2 0 d 3 0 . 00 bsc d 1 2 8 .00 bs c e 0 . 50 bsc e e1 l 0.4 5 0.6 0 0.7 5 l1 3 0. 00 bsc 2 8. 00 bsc 0.3 0 0.5 0 0.7 0 0 8 1 5 2 20 8 e d 1 d e e 1 4 5 7 4 5 7 3 3 6 0 . 1 0 c a - b d 0 . 0 8 c a - b d b 8 7 5 2 0 . 2 0 c a - b d 2 a a' s eati n g pla n e 0 . 0 8 c a a 1 0. 2 5 1 0 l 1 l b s ect i o n a - a' c 9 5 3 10 4 10 5 15 6 15 7 s i de vie w t o p vie w b o t t o m vie w 1 5 2 20 8 5 3 10 4 10 5 15 6 15 7 package ou t lin e, 2 08 le a d l q f p 28.0x28.0x1.7 mm lqr 208 r ev * * 002- 15151 ** document number: 002- 04727 rev. *b page 170 of 174 mb91590 series ? dimension of te qfp - 208(let208) l 1 1.00 re f l c 0.4 5 0.1 2 0.6 0 0.7 5 0.2 0 n o m . mi n . 2 8 . 0 0 b sc d 1 r 2 e 1 e 0 0.0 8 4 2 8 . 0 0 b sc 3 0 . 0 0 b sc d 2 a a 1 a 1.3 5 3 0 . 0 0 b sc 1.4 0 0.0 5 s y m b o l m ax. 8 0.2 0 1.4 5 1.7 0 0.1 5 d 2 d 3 e 2 e 3 9.90 re f 8.71 re f 9.90 re f 8.71 re f b 0.1 7 0.2 2 0.2 7 d i m e n sio n 1 r 0.0 8 e 0.50 bs c l 2 0.2 5 d 1 d 4 5 7 e 1 e 0.2 0 c a - b d 0.1 0 c a - b d d 3 d 2 e 3 e 2 a a 2 a 1 2 1 1 d e t a i l a e 0.0 8 c s eat i n g p l ane a a' b 0.0 8 c a - b d 8 s i d e v i ew t o p v i ew b o t t o m view b s e c t i o n a - a' c 1 0 l 1 l r 1 r 2 g a uge p l a n e d eta i l a l 2 exp o se d pad 28.0x28.0x1.7 mm l e t 208 r ev * a package ou t lin e, 20 8 lea d t e q f p 002 - 13651 *a document number: 002- 04727 rev. *b page 171 of 174 mb91590 series ? dimension of bga -320( bya320 ) 2 . d i m e n s io n s a nd t o l e r a nc es m e t h ods per asm e y14.5-2009 . t h is ou t lin e co n f orm s t o j ep95 , se c t io n 4 . 5 . 3 . ba ll p o s i t io n d es ig n a t io n pe r j ep 95, section 3, spp-010 . 4 . " e " r ep r ese n t s t h e so ld e r ball g r i d p i t ch . 5 . sy m bo l "m d " i s t h e ball m a t r ix s i z e i n th e " d " d i r e ct io n . sy m bo l "m e " i s t h e ball m a t r ix siz e i n th e " e " d i r e ct io n . n is t h e number o f popu la t ed so ld e r ball p o s i t io n s f o r m a tr i x si z e m d x m e . 6 . d i m e n s io n " b " i s m eas ur e d a t t h e maximum ball diam e t e r in a plane parall el t o d a tum c . 7 . " s d " a nd " se " a r e m eas ur e d w i t h respec t t o da t u ms a and b an d de f ine t h e po si t ion o f t h e cen t er s o l d e r ball i n th e o u t e r r o w . w h en t h ere i s an o dd number o f sold er balls in t h e ou t e r row , "sd " or "s e " = 0 . w h e n t h e r e is a n even n um ber o f s o l d e r balls i n t h e o u t e r r o w , "sd " = e d /2 a nd " se " = ee/ 2 . 1 . a ll d i m e n sio n s a r e i n m i ll i m e t e r s . 8 . a 1 c o rn e r t o be i d e n t i f i e d by cham f er, laser or ink m ark . m etallized m ark in den t a t io n o r o t h e r m ea n s . 9. " + " indicates th e th eoretical c e n t e r o f d ep o p u la t e d balls . n o t e s 10 . j e d e c spe c i f i c a t io n n o. r e f : n / a . no m . m i n . e 27 . 00 bs c d a 1 a 27 . 00 bs c sym b o l ma x . 2. 4 6 dim en s io n s 0. 3 5 d 1 e 1 m e m d n 2 0 2 0 3 2 0 b 0. 6 0 0. 9 0 0. 7 5 e e e d sd / s e 1 . 27 bs c 1 . 27 bs c 0 . 6 3 5 24 . 00 bs c 24 . 00 bs c d a 0.2 0 c 2 x e b 0.2 0 c 2 x p i n a1 c o rn er d 1 e 1 e d 1 2 3 4 5 6 7 8 9 1 0 1 1 a b c d e f g h j k l 32 0 x b 0.3 0 c a b 0.1 5 c 6 e e 7 7 a d eta i l a s i d e v i ew 0.2 0 c 0.1 5 c a 1 c d e t a i l a b o t t o m view t o p v i ew m n 1 2 1 3 p t 1 4 1 5 u v w y r 1 6 1 7 1 8 1 9 2 0 s d s e d 2 e 2 8 27 . 00x27 . 00x2 . 46 mm bya320 rev* * package ou t lin e, 3 20 b all f b g a 002 - 16414 ** document number: 002- 04727 rev. *b page 172 of 174 mb91590 series 14. major changes spansion publication number: mb91590_ds705 - 00010 page section change results revision 3.1 - - company name and layout design change see supplementary information as described in document definition. note: please see ?document history? about later revised information. document number: 002- 04727 rev. *b page 173 of 174 mb91590 series document history document title: mb91590 series fr family fr81s 32 - bit microcontroller document number: 002 - 04727 revision ecn orig. of change submission date description of change ** - nnas 06/19/2015 migrated to cypress and assigned document number 002 - 04712. no change to document contents or format . *a 5139796 nnas 02/19/2016 updated to cypress format. *b 5973870 hmiz 12/01/2017 1 2 . ordering information [improve] updated "ordering information" [improve] delete *2 : under consideration 13. package dimensions [improve] updated pkg figure for lqr208 , let208 and bya320 updated sales page. document n umber: 002- 04727 rev. *b december 1, 2017 page 174 of 174 mb91590 series sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturer?s representatives, and distributors. to find the office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/usb wireless connectivity cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 cypress developer community forums | wiced iot forums | projects | video s | blogs | training | components technical support cypress.com/support arm and cortex are registered trademarks of arm limited (or its subsidiaries) in the us and/or elsewhere . ? cypress semiconductor corporation, 201 5 - 2017 . this document is the property of cypress semiconductor corporation and its subsidiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intell ectual property laws and treaties of the unit ed states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this para graph, grant any license under its patents, copyrights, trademarks, or other intellectual property ri ghts. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypre ss governing the use of the software, then cypress hereby grants you a personal, non - exclusive, nontransferable license (without th e right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your or ganization, and (b) to di stribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardwar e product units, and (2) under those claims of cypress?s patents that are infringed by th e software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware products. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the e xtent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this document or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of any product or circuit describ ed in this document. any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and t est the functionality and safety of any application made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the ope ration of weapons, weapons systems, nuclear installations, life - support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution con trol or hazardous substances management, or other uses where the failure of t he device or system could cause personal injury, death, or property damage (?unintended uses?). a critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, o r to affect its safety or effectiveness. cypress is not liable, in whole or in part, and you shall and hereby do release cyp ress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall ind e mnify and hold cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez - usb, f - ram, and traveo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. othe r names and brands may be claimed as property of their respective owners. |
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